Patents by Inventor Su-Tsai Lu
Su-Tsai Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090008792Abstract: The 3D chip-stack package comprises a component-embedded plate and a side IC. The PCB has a plurality of conductive contacts. The component-embedded plate comprises a dielectric layer; an active component embedded in the dielectric layer, one surface of each active component exposed outside the dielectric layer, the active components having a plurality of TSVs (Through Silicon Via), one ends of the TSVs exposed outside the exposed surface, the other ends of the TSVs corresponding to the conductive contacts of the PCB; and an electrical circuit on the dielectric layer and in electrical connection between the other ends of the TSVs of the active component and the corresponding conductive contacts of the PCB, respectively. The side IC has a plurality of pads. The pads are electrically connected with the exposed ends of the TSVs of the active component.Type: ApplicationFiled: September 10, 2008Publication date: January 8, 2009Inventors: Cheng-Ta Ko, Su Tsai Lu
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Patent number: 7465603Abstract: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.Type: GrantFiled: November 13, 2007Date of Patent: December 16, 2008Assignee: Industrial Technology Research InstituteInventors: Yuan-Chang Huang, Tai-Hung Chen, Yao-Sheng Lin, Su-Tsai Lu
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Publication number: 20080305624Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: ApplicationFiled: August 19, 2008Publication date: December 11, 2008Inventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Patent number: 7459055Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: GrantFiled: October 16, 2006Date of Patent: December 2, 2008Assignee: Industrial Technology Research InstituteInventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Patent number: 7446421Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: GrantFiled: January 4, 2007Date of Patent: November 4, 2008Assignee: Industrial Technology Research InstituteInventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Patent number: 7423348Abstract: A chip structure including a chip, a passivation layer, an elastic layer and a metal layer is provided, with a bump disposed on the metal layer for electrically connecting a bonding pad of the chip. The passivation layer and the elastic layer are covering an active surface of the chip, and have an opening respectively for exposing top surface of the bonding pad, wherein the elastic layer is utilized to make the bump being heat-pressed onto a contact of a substrate with an enhanced electrical performance, and the elastic layer is made of for example polyimide or other macromolecule polymer. Moreover, the chip structure further includes a plurality of elastic granular structures at the bottom of the bump to enhance the bonding reliability of the bump.Type: GrantFiled: December 19, 2005Date of Patent: September 9, 2008Assignee: Industrial Technology Research InstituteInventor: Su-Tsai Lu
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Publication number: 20080211092Abstract: An electronic assembly comprising a first substrate, a number of bonds on the first substrate, a second substrate spaced apart from the first substrate, a number of bumps on the second substrate, each of the bumps including an insulating body and a conductive portion, the conductive portion extending from a top surface of the insulating body via at least one sidewall of the insulating body toward the second substrate, and an adhesive between the first substrate and the second substrate, the adhesive including an insulating layer and a conductive layer, the insulating layer and the conductive layer being laminated with respect to each other, wherein the insulating layer is positioned closer to the first substrate than the conductive layer.Type: ApplicationFiled: January 25, 2008Publication date: September 4, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Su-Tsai LU
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Patent number: 7378746Abstract: A composite bump suitable for disposing on a substrate pad is provided. The composite bump includes a compliant body and an outer conductive layer. The coefficient of thermal expansion (CTE) of the compliant body is between 5 ppm/° C. and 200 ppm/° C. The outer conductive layer covers the compliant body and is electrically connected to the pad. The compliant body can provide a stress buffering effect for a bonding operation. Furthermore, by setting of the CTE of the compliant body within a preferable range, damages caused by thermal stress are reduced while the bonding effect is enhanced.Type: GrantFiled: March 10, 2006Date of Patent: May 27, 2008Assignee: Industrial Technology Research InstituteInventors: Ji-Cheng Lin, Yao-Sheng Lin, Shyh-Ming Chang, Su-Tsai Lu, Hsien-Chie Cheng, Tai-Hong Chen
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Publication number: 20080081395Abstract: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.Type: ApplicationFiled: November 13, 2007Publication date: April 3, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Chang Huang, Tai-Hung Chen, Yao-Sheng Lin, Su-Tsai Lu
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Patent number: 7317235Abstract: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.Type: GrantFiled: March 18, 2005Date of Patent: January 8, 2008Assignee: Industrial Technology Research InstituteInventors: Yuan-Chang Huang, Tai-Hung Chen, Yao-Sheng Lin, Su-Tsai Lu
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Publication number: 20070210457Abstract: A composite bump suitable for disposing on a substrate pad is provided. The composite bump includes a compliant body and an outer conductive layer. The coefficient of thermal expansion (CTE) of the compliant body is between 5 ppm/° C. and 200 ppm/° C. The outer conductive layer covers the compliant body and is electrically connected to the pad. The compliant body can provide a stress buffering effect for a bonding operation. Furthermore, by setting of the CTE of the compliant body within a preferable range, damages caused by thermal stress are reduced while the bonding effect is enhanced.Type: ApplicationFiled: March 10, 2006Publication date: September 13, 2007Inventors: Ji-Cheng Lin, Yao-Sheng Lin, Shyh-Ming Chang, Su-Tsai Lu, Hsien-Chie Cheng, Tai-Hong Chen
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Patent number: 7239027Abstract: A bonding structure of device packaging includes a first substrate and a second substrate. The surfaces of the first substrate have metal pads and a first bonding layer connected to the second substrate whose surfaces have a second bonding layer and electrodes. The first bonding layer is combined with the second bonding layer, and the metal pads are in electrical communications with the electrodes. The second substrate may be a flexible substrate to decrease the strain between the first substrate and the second substrate.Type: GrantFiled: February 2, 2005Date of Patent: July 3, 2007Assignee: Industrial Technology Research InstituteInventor: Su-Tsai Lu
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Publication number: 20070122635Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: ApplicationFiled: January 4, 2007Publication date: May 31, 2007Inventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Publication number: 20070056163Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: ApplicationFiled: October 16, 2006Publication date: March 15, 2007Inventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Publication number: 20070052110Abstract: A chip structure including a chip, a passivation layer, an elastic layer and a metal layer is provided, with a bump disposed on the metal layer for electrically connecting a bonding pad of the chip. The passivation layer and the elastic layer are covering an active surface of the chip, and have an opening respectively for exposing top surface of the bonding pad, wherein the elastic layer is utilized to make the bump being heat-pressed onto a contact of a substrate with an enhanced electrical performance, and the elastic layer is made of for example polyimide or other macromolecule polymer. Moreover, the chip structure further includes a plurality of elastic granular structures at the bottom of the bump to enhance the bonding reliability of the bump.Type: ApplicationFiled: December 19, 2005Publication date: March 8, 2007Inventor: Su-Tsai Lu
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Patent number: 7183494Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: GrantFiled: April 20, 2004Date of Patent: February 27, 2007Assignee: Industrial Technology Research InstituteInventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Publication number: 20060078715Abstract: A bonding structure of device packaging includes a first substrate and a second substrate. The surfaces of the first substrate have metal pads and a first bonding layer connected to the second substrate whose surfaces have a second bonding layer and electrodes. The first bonding layer is combined with the second bonding layer, and the metal pads are in electrical communications with the electrodes. The second substrate may be a flexible substrate to decrease the strain between the first substrate and the second substrate.Type: ApplicationFiled: February 2, 2005Publication date: April 13, 2006Inventor: Su-Tsai Lu
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Publication number: 20060030079Abstract: A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.Type: ApplicationFiled: March 18, 2005Publication date: February 9, 2006Inventors: Yuan-Chang Huang, Tai-Hung Chen, Yao-Sheng Lin, Su-Tsai Lu
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Publication number: 20050112340Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: ApplicationFiled: April 20, 2004Publication date: May 26, 2005Inventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang