Abstract: Methods, systems, and devices for error correction code (ECC) coverage extension in a memory system are described. In a first technique, the memory system may correct, using a first ECC scheme, data bits read from a first memory die that has failed, the data bits included in a first codeword protected by the first ECC scheme. The memory system may generate, using a second ECC scheme and after correcting the data bits using the first ECC scheme, a second codeword that includes the data bits based on the memory system having a threshold quantity of failed memory dies. The memory system may write the data bits of the second codeword to a second memory die previously used to store parity bits for the first codeword.

Abstract: Systems and methods are disclosed, including a memory system that includes a memory array and a memory controller. The memory array includes memory cells that are included in multiple memory dies. The memory controller includes a cyclic redundancy check (CRC) encoder configured to determine a CRC code using a data word received by the memory controller; and a Bose-Chaudri-Hocqenghem (BCH) encoder configured to determine a BCH code using the data word and the CRC code. The memory controller is configured to store the data word in the memory array and store the BCH code and the CRC code in the memory array in association with the data word.

Abstract: Methods, memory devices, and systems for utilizing DDR5 DRAM dice without SEC parity bits, while still providing chipkill protection and RAS performance are described. The disclosed devices utilize a solution based upon locked RAID (LRAID) which omits the on-die SEC bits but retains RAS protections including chipkill protections. The system achieves this protection by replacing the Reed-Solomon parity bits with RAID parity bits, CRC bits, end-to-end SEC bits, and an end-to-end CRC. The SEC protection is enabled, in some examples, by a memory controller, such as by an on-ASIC memory controller making this an on-ASIC SEC rather than an on-die SEC.

Abstract: Devices and techniques that provide a fail visibility in a memory device are described herein. A memory system includes a first non-volatile memory to store error data; a second memory to store failure data; a random access memory device; and controller circuitry configured to: set a test mode in the random access memory device; read a row from a memory array of the random access memory device, the row including data bits and parity bits; use the parity bits to identify an error in the data bits; store an indication of the error in the first non-volatile memory; and store an indication of accumulated errors in the second memory.

Abstract: Systems and methods are disclosed, including prefetching, by a memory controller of a memory system of the computing system, at least two cache lines as a combined cache line in response to a memory access request from a host system of the computing system; and performing, by the memory controller, reduced chip fail error recovery to detect errors on data of the combined cache line.

Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

Abstract: Methods, memory devices, and systems for utilizing DDR5 DRAM dice without SEC parity bits, while still providing chipkill protection and RAS performance are described. The disclosed devices utilize a solution based upon locked RAID (LRAID) which omits the on-die SEC bits but retains RAS protections including chipkill protections. The system achieves this protection by replacing the Reed-Solomon parity bits with RAID parity bits, CRC bits, end-to-end SEC bits, and an end-to-end CRC. The SEC protection is enabled, in some examples, by a memory controller, such as by an on-ASIC memory controller making this an on-ASIC SEC rather than an on-die SEC.

Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

Abstract: A system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: receiving a request to access data; identifying a location among a plurality of locations on a memory partition, among a plurality of memory partitions of the memory, by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and performing an operation regarding the data at the identified location on the memory partition.

Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

Abstract: In some implementations, a memory controller may retrieve, via a first access operation, a block of user data and cyclic redundancy check (CRC) information associated with the block of user data, wherein the block of user data is retrieved using the one or more data pins, and wherein the CRC information is retrieved using one or more data mask inversion pins. The memory controller may determine, using the block of user data and the CRC information, whether the block of user data includes one or more bit errors. The memory controller may determine, based on whether the block of user data includes the one or more bit errors, whether to perform at least one of retrieving, via a second access operation, error correction information associated with the block of user data, or initiating a redundant array of independent disks error correction operation associated with the block of user data.

Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

Abstract: An integrated circuit device includes encryption circuitry to encrypt a data packet and scheduler circuitry to receive the encrypted data packet from the encryption circuitry. The scheduler circuitry monitors a duration of time associated with egress of the encrypted data packet, holds the encrypted data packet until the duration of time matches a threshold duration of time, and transmits the encrypted data packet in response to the duration of time matching the threshold duration of time.

Abstract: A system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: partitioning the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and performing an operation regarding the data at the identified location on the memory partition.

Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.

Abstract: A system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: partitioning the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and performing an operation regarding the data at the identified location on the memory partition.

Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.