Patents by Inventor Su Wei Lim
Su Wei Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11663154Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: GrantFiled: April 15, 2022Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20230026906Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.Type: ApplicationFiled: August 12, 2022Publication date: January 26, 2023Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Patent number: 11533170Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.Type: GrantFiled: March 28, 2019Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Reouven Elbaz, Hooi Kar Loo, Poh Thiam Teoh, Su Wei Lim, Patrick D. Maloney, Santosh Ghosh
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Publication number: 20220350769Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: ApplicationFiled: April 15, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Patent number: 11442876Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.Type: GrantFiled: May 30, 2019Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20220156211Abstract: Systems or methods of the present disclosure may provide a peripheral component interconnect express (PCIe) device that comprises a programmable fabric. The programmable fabric comprises multiple PCIe physical functions. The programmable fabric also includes switch circuitry having one or more embedded endpoints that dynamically hides or exposes one or more of the multiple PCIe physical functions from a bare metal mode host server without using a reset.Type: ApplicationFiled: December 22, 2021Publication date: May 19, 2022Inventors: Eng Hun Ooi, Su Wei Lim, Vaibhav Khamkar
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Patent number: 11308018Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: GrantFiled: September 9, 2020Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20220116373Abstract: An integrated circuit device includes encryption circuitry to encrypt a data packet and scheduler circuitry to receive the encrypted data packet from the encryption circuitry. The scheduler circuitry monitors a duration of time associated with egress of the encrypted data packet, holds the encrypted data packet until the duration of time matches a threshold duration of time, and transmits the encrypted data packet in response to the duration of time matching the threshold duration of time.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Choon Yip Soo, Su Wei Lim, Si Xing Saw, Markos Papadonikolakis
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Patent number: 11163717Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: GrantFiled: July 6, 2020Date of Patent: November 2, 2021Assignee: Intel CorporationInventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
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Method, apparatus, and system for power management on a CPU die via clock request messaging protocol
Patent number: 11016549Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.Type: GrantFiled: January 12, 2018Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Poh Thiam Teoh, Mikal C. Hunsaker, Su Wei Lim, Gim Chong Lee, Hooi Kar Loo, Shashitheren Kerisnan, Siang Lin Tan, Ming Chew Lee, Ngeok Kuan Wai, Li Len Lim -
Publication number: 20210056067Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: ApplicationFiled: July 6, 2020Publication date: February 25, 2021Applicant: Intel CorporationInventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
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Publication number: 20200409899Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: ApplicationFiled: September 9, 2020Publication date: December 31, 2020Applicant: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Patent number: 10776302Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: GrantFiled: April 2, 2019Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Patent number: 10706003Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: GrantFiled: February 4, 2019Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Michelle Jen, Daniel Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
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Publication number: 20190347218Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.Type: ApplicationFiled: May 30, 2019Publication date: November 14, 2019Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Publication number: 20190303338Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: ApplicationFiled: February 4, 2019Publication date: October 3, 2019Applicant: Intel CorporationInventors: Michelle Jen, Daniel Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
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Publication number: 20190229901Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.Type: ApplicationFiled: March 28, 2019Publication date: July 25, 2019Applicant: Intel CorporationInventors: Reouven Elbaz, Hooi Kar Loo, Poh Thiam Teoh, Su Wei Lim, Patrick D. Maloney, Santosh Ghosh
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Publication number: 20190227972Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.Type: ApplicationFiled: April 2, 2019Publication date: July 25, 2019Applicant: Intel CorporationInventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
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Patent number: 10311000Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.Type: GrantFiled: September 29, 2017Date of Patent: June 4, 2019Assignee: Intel CorporationInventors: Siang Lin Tan, Su Wei Lim, Ming Chew Lee, Ofer Nathan
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Publication number: 20190102335Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Siang Lin Tan, Su Wei Lim, Ming Chew Lee, Ofer Nathan