Patents by Inventor Su Wei Lim
Su Wei Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10248183Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.Type: GrantFiled: December 6, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
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Publication number: 20190095554Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Eng Hun Ooi, Su Wei Lim, Kuan Hua Tan, Prashanth Kalluraya
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Patent number: 10229080Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.Type: GrantFiled: July 17, 2015Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Ting Lok Song, Su Wei Lim, Mikal C. Hunsaker, Hooi Kar Loo
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Patent number: 10209911Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.Type: GrantFiled: September 16, 2014Date of Patent: February 19, 2019Assignee: INTEL CORPORATIONInventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan
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Publication number: 20190042155Abstract: Systems, apparatuses and methods may provide for technology to add non-address metadata to a memory address field of a transaction layer packet (TLP), wherein the non-address metadata includes one or more vendor-specific attributes. Additionally, the technology may coordinate between a transmitter and a receiver to prevent the TLP from violating an address boundary constraint associated with an interface. In one example, the address boundary constraint prohibits an address and length combination of the TLP from crossing a 4-KB boundary.Type: ApplicationFiled: May 14, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Eng Hun Ooi, Shrinivas Venkatraman, Kuan Hua Tan, Ang Li, Sahar Khalili, Su Wei Lim, Robert Royer, JR.
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METHOD, APPARATUS, AND SYSTEM FOR POWER MANAGEMENT ON A CPU DIE VIA CLOCK REQUEST MESSAGING PROTOCOL
Publication number: 20190041936Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.Type: ApplicationFiled: January 12, 2018Publication date: February 7, 2019Inventors: Poh Thiam Teoh, Mikal C. Hunsaker, Su Wei Lim, Gim Chong Lee, Hooi Kar Loo, Shashitheren Kerisnan, Siang Lin Tan, Ming Chew Lee, Ngeok Kuan Wai, Li Len Lim -
Patent number: 10198394Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: GrantFiled: October 1, 2016Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
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Patent number: 10146715Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: GrantFiled: January 24, 2017Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
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Patent number: 10127184Abstract: An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.Type: GrantFiled: September 27, 2016Date of Patent: November 13, 2018Assignee: Intel CorporationInventors: Eng Hun Ooi, Su Wei Lim
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Patent number: 9946676Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k?h, so that ?k/n? hard IP blocks provide h=n*p available hard IP data lanes. In that case, h?k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.Type: GrantFiled: March 26, 2015Date of Patent: April 17, 2018Assignee: Intel CorporationInventors: Mahesh Wagh, Zuoguo Wu, Venkatraman Iyer, Gerald S. Pasdast, Mark S. Birrittella, Ishwar Agarwal, Lip Khoon Teh, Su Wei Lim, Anoop Kumar Upadhyay
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Publication number: 20180089137Abstract: An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Inventors: Eng Hun OOI, Su Wei LIM
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Patent number: 9921987Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: GrantFiled: July 25, 2016Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
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Patent number: 9910814Abstract: Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.Type: GrantFiled: March 13, 2015Date of Patent: March 6, 2018Assignee: INTEL CORPORATIONInventors: Bryan L. Spry, Su Wei Lim, Mikal C. Hunsaker, Rohit R. Verma, Lily P. Looi, Ronald W. Swartz, Michael W. Leddige, Vui Yong Liew
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Publication number: 20170344512Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.Type: ApplicationFiled: October 1, 2016Publication date: November 30, 2017Inventors: Michelle Jen, Dan Froelich, Debendra Das Sharma, Bruce Tennant, Quinn Devine, Su Wei Lim
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Patent number: 9830292Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.Type: GrantFiled: August 26, 2015Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Mahesh Wagh, Su Wei Lim
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Patent number: 9753529Abstract: Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.Type: GrantFiled: May 18, 2016Date of Patent: September 5, 2017Assignee: INTEL CORPORATIONInventors: Mahesh Wagh, Su Wei Lim
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Publication number: 20170235701Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.Type: ApplicationFiled: December 24, 2014Publication date: August 17, 2017Applicant: INTEL CORPORATIONInventors: Akshay Pethe, Mahesh Wagh, David Harriman, Su Wei Lim, Debendra Das Sharma, Daniel Froelich, Venkatraman Iyer, James Jaussi, Zuoguo Wu
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Publication number: 20170132171Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: ApplicationFiled: January 24, 2017Publication date: May 11, 2017Applicant: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
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Patent number: 9619416Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: GrantFiled: March 25, 2015Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
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Publication number: 20170083079Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Applicant: Intel CorporationInventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim