Patents by Inventor Subhankar Panda
Subhankar Panda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111560Abstract: Embodiments herein relate to providing uniform servicing of workloads at a set of servers in a computer network. A platform determines and meets the performance requirements of a workload by scaling a performance capability of a group of processing units such as central processing units (CPUs) which are assigned to service the workload. This can involve increasing the power (P) state of one or more of the processing units to a highest P state in the group, so that every processing units in the group provides the same performance for a given workload. The platform can manage scaling of the processing units performance by reading a performance profile list which indicates minimum and maximum scaling points for programs that are executed to service the workload.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Subhankar Panda, Rupal M. Parikh, Gaurav Porwal, Raghavendra Nagaraj, Sagar C. Pawar, Prakash Pillai
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Patent number: 11687391Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.Type: GrantFiled: November 1, 2021Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Gaurav Porwal, Subhankar Panda, John G. Holm
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Publication number: 20230091969Abstract: Methods and apparatus relating to lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors are described. In an embodiment, a plurality of storage entries store error information to be detected at one or more physical lanes of an interface. Faulty lane detection logic circuitry determines which of the one or more physical lanes is faulty or more likely to be faulty based at least in part on the stored error information for the one or more physical lanes of the interface. The stored error information comprises historical error details for the one or more physical lanes of the interface. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventors: Gaurav Porwal, Theodros Yigzaw, Subhankar Panda, John Holm
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Patent number: 11573845Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.Type: GrantFiled: March 30, 2021Date of Patent: February 7, 2023Assignee: INTEL CORPORATIONInventors: Stalinselvaraj Jeyasingh, Subhankar Panda, David A. Locklear, Steven A. Filary, Christopher J. Stedman, Carlos Vallin
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Publication number: 20220326860Abstract: A dedicated bank-based error counter is provided for a respective bank of a Dynamic Random Access Memory (DRAM). The dedicated bank-based error counter for the bank is stored in memory resources. A Basic Input/Output System (BIOS) System Management Interrupt (SMI) handler triggers Adaptive Double Device Data Correction (ADDDC) bank sparing if the error count for the respective bank equals or exceeds a per bank ADDDC threshold.Type: ApplicationFiled: June 27, 2022Publication date: October 13, 2022Inventors: Jun LI, Subhankar PANDA, Gaurav PORWAL, Feiting WANYAN
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Publication number: 20220241300Abstract: The disclosure relates to compounds of the formula (I) and (II), pharmaceutical compositions comprising one or more such compounds, and methods for treating pulmonary infections with one or more such compounds (e.g., treating SARS-CoV, MERS-CoV or SARS-CoV-2).Type: ApplicationFiled: January 19, 2022Publication date: August 4, 2022Inventors: Courtney C. Aldrich, Subhankar Panda, Tej Poudel
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Publication number: 20220229714Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.Type: ApplicationFiled: November 1, 2021Publication date: July 21, 2022Inventors: Gaurav PORWAL, Subhankar PANDA, John G. HOLM
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Publication number: 20220196733Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Gaurav Porwal, Subhankar Panda, Theodros Yigzaw, John Holm
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Patent number: 11163623Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.Type: GrantFiled: May 4, 2020Date of Patent: November 2, 2021Assignee: Intel CorporationInventors: Gaurav Porwal, Subhankar Panda, John G. Holm
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Publication number: 20210286667Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to provide management of a connected hardware subsystem with respect to one or more of reliability, availability and serviceability, and coordinate the management of the connected hardware subsystem with respect to one or more of reliability, availability and serviceability between the connected hardware subsystem and a host. Other embodiments are disclosed and claimed.Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Applicant: Intel CorporationInventors: Theodros Yigzaw, John Holm, Subhankar Panda, Hugo Enrique Gonzalez Chavero, Satyaprakash Nanda, Omar Avelar Suarez, Guarav Porwal
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Publication number: 20210216392Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.Type: ApplicationFiled: March 30, 2021Publication date: July 15, 2021Applicant: INTEL CORPORATIONInventors: Stalinselvaraj Jeyasingh, Subhankar Panda, David A. Locklear, Steven A. Filary, Christopher J. Stedman, Carlos Vallin
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Patent number: 11061885Abstract: An embodiment of a semiconductor package apparatus may include technology to create a range search tree based on a data stream, cluster data from the data stream based on the range search tree and application of a modified density based spatial cluster of applications with noise scheme, and detect an anomaly in the data stream based on the clustered data. Other embodiments are disclosed and claimed.Type: GrantFiled: June 15, 2018Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Agnieszka Potulska, Piotr Tylenda, Subhankar Panda
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Patent number: 11016833Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.Type: GrantFiled: July 1, 2017Date of Patent: May 25, 2021Assignee: INTEL CORPORATIONInventors: Stalinselvaraj Jeyasingh, Subhankar Panda, David A. Locklear, Steven A. Filary, Christopher J. Stedman, Carlos Vallin
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Patent number: 10929232Abstract: A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.Type: GrantFiled: May 31, 2017Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Subhankar Panda, Sarathy Jayakumar, Gaurav Porwal, Theodros Yigzaw
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Patent number: 10824496Abstract: An apparatus and method for machine check bank reporting in a processor. For example, one embodiment includes a processor comprising: one or more cores to execute instructions and process data; a plurality of machine check architecture banks to store errors detected during execution of the instructions; error monitoring circuitry to detect the errors and responsively update the MCA banks; and a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing a first error in an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error; and one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent errors occurring after the first error.Type: GrantFiled: December 28, 2017Date of Patent: November 3, 2020Assignee: Intel CorporationInventors: Subhankar Panda, Gaurav Porwal, John G. Holm
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Patent number: 10824493Abstract: A mechanism for disambiguation of error logging during a warm reset is disclosed. A system agent detects an error occurring during bootstrapping of a processor package. The error occurs prior to initiation of a machine check system. A wide pulse event is initiated to signal a wide pulse register to store a wide pulse time stamp counter value. The wide pulse event also signals a lap register to store a lap time stamp counter value. The wide pulse register maintains the wide pulse time stamp counter value during a warm reset, and the lap register clears the lap time stamp counter value during the warm reset. The system agent obtains the wide pulse time stamp counter value and the lap time stamp counter value after bootstrapping is complete to determine an order of occurrence of the error relative to the warm reset.Type: GrantFiled: May 26, 2017Date of Patent: November 3, 2020Assignee: Intel CorporationInventors: Subhankar Panda, Gaurav Porwal
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Publication number: 20200301773Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.Type: ApplicationFiled: May 4, 2020Publication date: September 24, 2020Inventors: Gaurav PORWAL, Subhankar PANDA, John G. HOLM
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Patent number: 10671465Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.Type: GrantFiled: November 28, 2016Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Gaurav Porwal, Subhankar Panda, John G. Holm
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Publication number: 20190205201Abstract: An apparatus and method for machine check bank reporting in a processor. For example, one embodiment includes a processor comprising: one or more cores to execute instructions and process data; a plurality of machine check architecture banks to store errors detected during execution of the instructions; error monitoring circuitry to detect the errors and responsively update the MCA banks; and a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing a first error in an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error; and one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent errors occurring after the first error.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: SUBHANKAR PANDA, GAURAV PORWAL, JOHN G. HOLM
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Publication number: 20190042618Abstract: An embodiment of a semiconductor package apparatus may include technology to create a range search tree based on a data stream, cluster data from the data stream based on the range search tree and application of a modified density based spatial cluster of applications with noise scheme, and detect an anomaly in the data stream based on the clustered data. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 15, 2018Publication date: February 7, 2019Inventors: Agnieszka Potulska, Piotr Tylenda, Subhankar Panda