Patents by Inventor Subhankar Panda

Subhankar Panda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10824493
    Abstract: A mechanism for disambiguation of error logging during a warm reset is disclosed. A system agent detects an error occurring during bootstrapping of a processor package. The error occurs prior to initiation of a machine check system. A wide pulse event is initiated to signal a wide pulse register to store a wide pulse time stamp counter value. The wide pulse event also signals a lap register to store a lap time stamp counter value. The wide pulse register maintains the wide pulse time stamp counter value during a warm reset, and the lap register clears the lap time stamp counter value during the warm reset. The system agent obtains the wide pulse time stamp counter value and the lap time stamp counter value after bootstrapping is complete to determine an order of occurrence of the error relative to the warm reset.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Subhankar Panda, Gaurav Porwal
  • Patent number: 10824496
    Abstract: An apparatus and method for machine check bank reporting in a processor. For example, one embodiment includes a processor comprising: one or more cores to execute instructions and process data; a plurality of machine check architecture banks to store errors detected during execution of the instructions; error monitoring circuitry to detect the errors and responsively update the MCA banks; and a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing a first error in an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error; and one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent errors occurring after the first error.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Subhankar Panda, Gaurav Porwal, John G. Holm
  • Publication number: 20200301773
    Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.
    Type: Application
    Filed: May 4, 2020
    Publication date: September 24, 2020
    Inventors: Gaurav PORWAL, Subhankar PANDA, John G. HOLM
  • Patent number: 10671465
    Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Gaurav Porwal, Subhankar Panda, John G. Holm
  • Publication number: 20190205201
    Abstract: An apparatus and method for machine check bank reporting in a processor. For example, one embodiment includes a processor comprising: one or more cores to execute instructions and process data; a plurality of machine check architecture banks to store errors detected during execution of the instructions; error monitoring circuitry to detect the errors and responsively update the MCA banks; and a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing a first error in an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error; and one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent errors occurring after the first error.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: SUBHANKAR PANDA, GAURAV PORWAL, JOHN G. HOLM
  • Publication number: 20190042618
    Abstract: An embodiment of a semiconductor package apparatus may include technology to create a range search tree based on a data stream, cluster data from the data stream based on the range search tree and application of a modified density based spatial cluster of applications with noise scheme, and detect an anomaly in the data stream based on the clustered data. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 15, 2018
    Publication date: February 7, 2019
    Inventors: Agnieszka Potulska, Piotr Tylenda, Subhankar Panda
  • Publication number: 20190004887
    Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.
    Type: Application
    Filed: July 1, 2017
    Publication date: January 3, 2019
    Applicant: INTEL CORPORATION
    Inventors: Stalinselvaraj Jeyasingh, Subhankar Panda, David A. Locklear, Steven A. Filary, Christopher J. Stedman, Carlos Vallin
  • Publication number: 20180349231
    Abstract: A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Applicant: Intel Corporation
    Inventors: Subhankar Panda, Sarathy Jayakumar, Gaurav Porwal, Theodros Yigzaw
  • Publication number: 20180341537
    Abstract: A mechanism for disambiguation of error logging during a warm reset is disclosed. A system agent detects an error occurring during bootstrapping of a processor package. The error occurs prior to initiation of a machine check system. A wide pulse event is initiated to signal a wide pulse register to store a wide pulse time stamp counter value. The wide pulse event also signals a lap register to store a lap time stamp counter value. The wide pulse register maintains the wide pulse time stamp counter value during a warm reset, and the lap register clears the lap time stamp counter value during the warm reset. The system agent obtains the wide pulse time stamp counter value and the lap time stamp counter value after bootstrapping is complete to determine an order of occurrence of the error relative to the warm reset.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Inventors: Subhankar Panda, Gaurav Porwal
  • Publication number: 20180150345
    Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Applicant: Intel Corporation
    Inventors: Gaurav Porwal, Subhankar Panda, John G. Holm
  • Patent number: 8396297
    Abstract: Methods and systems to identify image pixels as edge pixels using fractal signatures associated with the image pixels. Fractal signatures may include one or more of a variety of fractal dimensions. A fractal dimension of a pixel may be generated from an array of pixels that include the pixel, from x and y coordinates and one or more of luminosity values and color values associated with pixels in the array of pixels. Pixels may be identified as edge pixels when their corresponding fractal signatures are equal to or greater than a fractal signature threshold. The fractal signature threshold may be generated in a supervised fashion.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: March 12, 2013
    Assignee: Intel Corporation
    Inventor: Subhankar Panda
  • Patent number: 8209551
    Abstract: Methods and apparatus for accessing a redundant array of independent drives (RAID) storage device are disclosed. In some embodiments file data is broken into multiple segments. A cryptographic operation is performed on one or more segments to generate encrypted segment(s). One or more parity syndrome is computed from the encrypted segment(s) and the unencrypted segment(s). The encrypted segment(s), the unencrypted segment(s) and the parity syndrome(s) are striped onto different individual drives. Since the cryptographic operation is not performed on all the segments, it may also be performed concurrently with computing of parity syndrome(s) from other unencrypted segments.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Yen Hsiang Chew, Subhankar Panda
  • Publication number: 20100031060
    Abstract: Methods and apparatus for accessing a redundant array of independent drives (RAID) storage device are disclosed. In some embodiments file data is broken into multiple segments. A cryptographic operation is performed on one or more segments to generate encrypted segment(s). One or more parity syndrome is computed from the encrypted segment(s) and the unencrypted segment(s). The encrypted segment(s), the unencrypted segment(s) and the parity syndrome(s) are striped onto different individual drives. Since the cryptographic operation is not performed on all the segments, it may also be performed concurrently with computing of parity syndrome(s) from other unencrypted segments.
    Type: Application
    Filed: February 15, 2008
    Publication date: February 4, 2010
    Inventors: YEN HSIANG CHEW, Subhankar Panda
  • Publication number: 20090297055
    Abstract: Methods and systems to identify image pixels as edge pixels using fractal signatures associated with the image pixels. Fractal signatures may include one or more of a variety of fractal dimensions. A fractal dimension of a pixel may be generated from an array of pixels that include the pixel, from x and y coordinates and one or more of luminosity values and color values associated with pixels in the array of pixels. Pixels may be identified as edge pixels when their corresponding fractal signatures are equal to or greater than a fractal signature threshold. The fractal signature threshold may be generated in a supervised fashion.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 3, 2009
    Inventor: Subhankar Panda
  • Publication number: 20090248835
    Abstract: A method, system, and computer readable medium are disclosed. In one embodiment the method includes initiating a data transfer from a first computing device to a second computing device. Then the method continues by designating a third computing device to offload at least a portion of the data associated with the data transfer. Additionally, the method stores the offloaded portion of the data on the designated third computing device for a period of time. Finally, the method concludes by sending the data stored on the third computing device to the second computing device after the period of time.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Subhankar Panda, Yong Joo Lee
  • Publication number: 20080077750
    Abstract: In general, in one aspect, the disclosure describes a processor having a central processing unit, a memory controller unit and a shared bus. The CPU can execute software programs to control operation of the processor and can initiate a memory write operation. The memory controller unit includes at least one register to capture parameters related to the memory write operation. The memory write operation parameters are written to the at least one register in said memory controller unit. The memory controller unit utilizes the memory write operation parameters to perform the memory write operation.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Inventor: Subhankar Panda