Patents by Inventor Subhas Bothra

Subhas Bothra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8274353
    Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: September 25, 2012
    Assignee: Broadcom Corporation
    Inventors: Carol Barrett, Tom McKay, Subhas Bothra
  • Patent number: 8270629
    Abstract: A system and method allow for safe use of headphones that include a microphone when using the headphones with a cellular phone, a music device, or the like. A desired audio signal, e.g., a voice of a caller or music, is discontinued when a microphone associated with the headphones picks up either a change in ambient noise or a particular type of ambient noise, e.g., an ambulance, a police car, a fire truck, someone yelling, brakes squealing, or the like. During this state, the headphones output either an audible alert signal, the ambient noise, or a pre-stored signal that states “fire,” “police,”, “yelling,” etc. In this way, a person can safely talk on the phone or listen to music when walking or driving, while still being cognizant of what is going on around them.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: September 18, 2012
    Assignee: Broadcom Corporation
    Inventors: Subhas Bothra, Louis Pandula
  • Publication number: 20110163831
    Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 7, 2011
    Applicant: BROADCOM CORPORATION
    Inventors: Carol Barrett, Tom McKay, Subhas Bothra
  • Patent number: 7911310
    Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: March 22, 2011
    Assignee: Broadcom Corporation
    Inventors: Carol Barrett, Tom McKay, Subhas Bothra
  • Patent number: 7614024
    Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: November 3, 2009
    Assignee: Broadcom Corporation
    Inventor: Subhas Bothra
  • Publication number: 20090127654
    Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.
    Type: Application
    Filed: January 26, 2009
    Publication date: May 21, 2009
    Applicant: Broadcom Corporation
    Inventors: Carol Barrett, Tom McKay, Subhas Bothra
  • Patent number: 7489221
    Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: February 10, 2009
    Assignee: Broadcom Corporation
    Inventors: Carol Barrett, Tom McKay, Subhas Bothra
  • Patent number: 7434189
    Abstract: Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: October 7, 2008
    Assignee: Broadcom Corporation
    Inventors: Donald Baumann, Subhas Bothra
  • Publication number: 20070210775
    Abstract: An integrated circuit power supply includes a DC-to-DC converter and a low drop-out voltage regulator. The DC-to-DC converter efficiently performs voltage conversion and provides power to the low-dropout voltage regulator. The low-dropout voltage regulator rejects noise and regulates an output voltage. The combination of the DC-to-DC converter and a low-dropout voltage regulator provides high-efficiency voltage conversion and noise rejection.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Applicant: Broadcom Corporation
    Inventors: Subhas Bothra, Louis Pandula
  • Publication number: 20070090401
    Abstract: Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventors: Donald Baumann, Subhas Bothra
  • Publication number: 20070092087
    Abstract: A system and method allow for safe use of headphones that include a microphone when using the headphones with a cellular phone, a music device, or the like. A desired audio signal, e.g., a voice of a caller or music, is discontinued when a microphone associated with the headphones picks up either a change in ambient noise or a particular type of ambient noise, e.g., an ambulance, a police car, a fire truck, someone yelling, brakes squealing, or the like. During this state, the headphones output either an audible alert signal, the ambient noise, or a pre-stored signal that states “fire,” “police,”, “yelling,” etc. In this way, a person can safely talk on the phone or listen to music when walking or driving, while still being cognizant of what is going on around them.
    Type: Application
    Filed: October 24, 2005
    Publication date: April 26, 2007
    Applicant: Broadcom Corporation
    Inventors: Subhas Bothra, Louis Pandula
  • Publication number: 20070083833
    Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout.
    Type: Application
    Filed: October 6, 2005
    Publication date: April 12, 2007
    Inventor: Subhas Bothra
  • Publication number: 20060273874
    Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.
    Type: Application
    Filed: August 15, 2006
    Publication date: December 7, 2006
    Applicants: Broadcom Corporation, Zeevo, Inc.
    Inventors: Carol Barrett, Tom McKay, Subhas Bothra
  • Patent number: 7095307
    Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: August 22, 2006
    Assignee: Broadcom Corporation
    Inventors: Carol Barrett, Tom McKay, Subhas Bothra
  • Patent number: 6916525
    Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: July 12, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Subhas Bothra, Milind G. Weling
  • Patent number: 6787908
    Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: September 7, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Steven L Skala, Subhas Bothra, Emmanuel Demuizon
  • Patent number: 6756316
    Abstract: Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: June 29, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Subhas Bothra, Harlan Lee Sur, Jr.
  • Patent number: 6717232
    Abstract: A semiconductor inductor and a method for making a semiconductor inductor are provided. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench within the oxide layer. The oxide layer is also etched to form a first inductor trench within the oxide layer such that the first inductor trench is defined in an inductor geometry. The oxide layer is then etched to form at least one via in the interconnect metallization trench and a second inductor trench over the first inductor trench in the oxide layer. The second inductor trench also has the inductor geometry. After the oxide layer is etched, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with copper. The semiconductor inductor is configured to have a low resistance and a high quality factor.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: April 6, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Subhas Bothra
  • Publication number: 20040058543
    Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.
    Type: Application
    Filed: September 19, 2003
    Publication date: March 25, 2004
    Inventors: Subhas Bothra, Milind G. Weling
  • Patent number: 6710425
    Abstract: A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed between selected first and second metallic interconnections which are separated by an insulating intermetallic oxide layer. A first metal-dielectric-metal layer capacitor is created over and with a portion of the first metallic interconnection and a second metal-dielectric-metal layer capacitor is created under and with a portion of the second metallic interconnection. A first metal via through the insulating intermetallic oxide layer connects the first metal-dielectric-metal layer capacitor and the second metal-dielectric-metal layer capacitor to form a first terminal of the capacitor structure and a second metal via through the insulating intermetallic oxide layer connects the first metallic interconnection portion and the second metallic interconnection portion to form a second terminal of the capacitor structure.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: March 23, 2004
    Assignee: Zeevo, Inc.
    Inventor: Subhas Bothra