Abstract: A method for manufacturing probe tips suitable for use in an atomic force microscope (AFM) or scanning tunneling microscope (STM) begins by depositing a layer of a first material over a substrate and then patterning the layer of the first material to define apertures wherever probe tips are to be formed. Next, a layer of a second material is deposited using an unbiased high density plasma chemical vapor deposition (HDPCVD) process to form sharp probe tips in the apertures in the layer of the first material. The HDPCVD process also forms a sacrificial layer of the second material on top of the portions of the first material not removed by the patterning step. The sacrificial layer at least partially overhangs the apertures in the first material, forming a shadow mask during the deposition process which gives rise to a sharp probe profile.

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract: The present invention provides methods of determining a smallest dimension of a fabricated device on a semiconductor substrate, methods of determining width of a structure comprising a refractory metal silicide, methods of determining parameters of a semiconductor device comprising a refractory metal silicide, and methods of determining width of an insulative spacer of a semiconductor device.

Abstract: A device and method for determining parasitic resistances in a metal oxide silicon field effect transistor (MOSFET). In one embodiment of the present invention, respective total resistances between a plurality of pairs of varyingly spaced apart first contacts of a first test structure are measured. The contact resistance between the plurality of first contacts and a first silicided region and a sheet resistance per unit length of the first silicided region are calculated from the previously measured respective total resistances. Next, respective total resistances between a plurality of pairs of varyingly spaced apart second contacts of a second test structure are measured. The present invention then calculates from the previously measured respective total resistances various resistance components contributing to a total resistance between any pair of the plurality of second contacts.

Abstract: Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7.

Abstract: Disclosed is a chemical mechanical polishing system. The system includes a mechanical arm and a carrier body that is configured to be coupled to the mechanical arm. The carrier body has a recessed portion for retaining a semiconductor wafer. The recessed portion has a carrier film that is in direct contact with a back side of the semiconductor wafer. The system further includes a plurality of pressure rings that are defined in the carrier body, such that the plurality of pressure rings are in direct contact with the carrier film. Each of the plurality of pressure rings are used to apply a selected pressure to the carrier film, such that the carrier film produces a back pressure against the back side of the semiconductor wafer. The back pressure is configured to be consistent with the selected pressure that is applied to each of the plurality of pressure rings.

Abstract: A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract: The present invention is a micro-electromechanical voltage shifter. According to one embodiment, the voltage shifter of the present invention comprises a capacitor and micro-electromechanical means for changing a capacitance of the capacitor. The capacitor is initially charged and then electrically isolated. When the capacitance is altered, potential difference across the capacitor is shifted accordingly. In one embodiment of the present invention, the micro-electromechanical means includes a gear wheel driven by a micro-motor. The gear wheel preferably includes a plurality of teeth protruding along a circumference of the gear wheel. Further, the gear wheel is positioned next to the capacitor and configured to move the teeth into and out of a gap between the capacitor plates. As the teeth is preferably made of dielectric material, the voltage across the capacitor is changed as a tooth enters or leaves the gap. In another embodiment, the teeth may be made of a conducting material.

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer.

Abstract: A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment structure is constructed so that its surface will retain sufficient topography to enable the alignment apparatus to properly align.

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract: Disclosed is a method for making a high resistive structure in a salicided process. The method includes providing a substrate including at least one active device having diffusion regions and a polysilicon gate structure. Depositing a metallization layer over the substrate including at least one active device. Annealing the substrate to cause at least part of metallization layer to form a metallization silicided layer over the substrate that includes the at least one active device. Preferably, the metallization silicided layer lying over the diffusion regions and the polysilicon gate produces a substantially decreased level of sheet resistance. The method also includes forming a mask over the metallization silicided layer, and the mask being configured to leave a portion of the metallization silicided layer that overlies at least one active device exposed.

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and nonsacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer.

Abstract: A method of forming sharp oxide peaks on the surface of a semiconductor wafer for the purpose of conditioning polishing pads used during a Chemical Mechanical Polishing process is disclosed. In order to create oxide peaks on the surface of a wafer, additional elements are added to a trace layer of the wafer. An oxide layer is deposited over the additional elements using an Electron Cyclotron Resonance Chemical Vapor Deposition process, which includes a sputtering step, in order to create sharp peaks in the oxide layer over the additional lines. In some embodiments, the additional elements may be formed from a multiplicity of rectangular blocks over which pyramid-like oxide peaks are created. In others, they may be formed from a multiplicity of rectangular blocks connected by narrow lines over which pyramid-like oxide peaks and knife-edged peaks, respectively, are created.

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract: Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%.