Patents by Inventor Subhash Balakrishna Pillai
Subhash Balakrishna Pillai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11816338Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: GrantFiled: September 28, 2022Date of Patent: November 14, 2023Assignee: Western Digital Technologies, Inc.Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
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Publication number: 20230017605Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: ApplicationFiled: September 28, 2022Publication date: January 19, 2023Applicant: Western Digital Technologies, Inc.Inventors: Yun-Tzuo LAI, Haining LIU, Subhash Balakrishna PILLAI
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Patent number: 11500780Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: GrantFiled: October 30, 2020Date of Patent: November 15, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Caesar Cheuk-Chow Cheung, Haining Liu, Subhash Balakrishna Pillai
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Patent number: 11487437Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: GrantFiled: April 5, 2021Date of Patent: November 1, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
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Patent number: 11474709Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: January 20, 2021Date of Patent: October 18, 2022Assignee: Western Digital Technologies, Inc.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20210223965Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Yun-Tzuo LAI, Haining LIU, Subhash Balakrishna PILLAI
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Patent number: 11048589Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: GrantFiled: April 17, 2019Date of Patent: June 29, 2021Assignee: Western Digital Technologies, Inc.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20210141542Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Patent number: 10990296Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: GrantFiled: November 25, 2019Date of Patent: April 27, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES. INC.Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
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Publication number: 20210049106Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: ApplicationFiled: October 30, 2020Publication date: February 18, 2021Inventors: Caesar Cheuk-Chow CHEUNG, Haining LIU, Subhash Balakrishna PILLAI
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Patent number: 10901632Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: July 26, 2019Date of Patent: January 26, 2021Assignee: WESTERN DITIGAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Patent number: 10846238Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: GrantFiled: June 27, 2019Date of Patent: November 24, 2020Assignee: Western Digital Technologies, Inc.Inventors: Caesar Cheuk-Chow Cheung, Haining Liu, Subhash Balakrishna Pillai
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Publication number: 20200097187Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Inventors: Yun-Tzuo LAI, Haining LIU, Subhash Balakrishna PILLAI
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Patent number: 10503412Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: GrantFiled: May 24, 2017Date of Patent: December 10, 2019Assignee: Western Digital Technologies, Inc.Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
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Publication number: 20190347018Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Publication number: 20190317700Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Inventors: Caesar Cheuk-Chow CHEUNG, Haining LIU, Subhash Balakrishna PILLAI
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Publication number: 20190251028Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: ApplicationFiled: April 17, 2019Publication date: August 15, 2019Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Patent number: 10380028Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.Type: GrantFiled: December 30, 2016Date of Patent: August 13, 2019Assignee: Western Digital Technologies, Inc.Inventors: Caesar Cheuk-Chow Cheung, Haining Liu, Subhash Balakrishna Pillai
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Patent number: 10379758Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: July 31, 2017Date of Patent: August 13, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Patent number: 10289551Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: GrantFiled: May 11, 2017Date of Patent: May 14, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai