Patents by Inventor Subhash M. Joshi
Subhash M. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170040218Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Publication number: 20160351716Abstract: The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.Type: ApplicationFiled: July 11, 2016Publication date: December 1, 2016Applicant: Intel CorporationInventors: Subhash M. Joshi, Michael L. Hattendorf
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Patent number: 9508821Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: December 23, 2015Date of Patent: November 29, 2016Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Publication number: 20160308032Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.Type: ApplicationFiled: December 23, 2013Publication date: October 20, 2016Inventors: Glenn A. GLASS, Anand s. MURTHY, Daniel B. AUBERTINE, Subhash M. JOSHI
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Patent number: 9466565Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: June 4, 2015Date of Patent: October 11, 2016Assignee: Intel CorporationInventors: Mark T Bohr, Tahir Ghani, Nadia M. Rahhai-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 9425316Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: GrantFiled: December 17, 2015Date of Patent: August 23, 2016Assignee: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Patent number: 9419106Abstract: The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.Type: GrantFiled: September 30, 2011Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Subhash M. Joshi, Michael Hattendorf
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Publication number: 20160155815Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: December 23, 2015Publication date: June 2, 2016Inventors: Mark T. BOHR, Tahir GHANI, Nadia M. RAHHAL-ORABI, Subhash M. JOSHI, Joseph M. STEIGERWALD, Jason W. KLAUS, Jack HWANG, Ryan MACKIEWICZ
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Publication number: 20160111532Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: ApplicationFiled: December 17, 2015Publication date: April 21, 2016Applicant: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Publication number: 20150270216Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: June 4, 2015Publication date: September 24, 2015Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhai-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 9093513Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: March 5, 2013Date of Patent: July 28, 2015Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Patent number: 9054178Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: GrantFiled: February 6, 2014Date of Patent: June 9, 2015Assignee: Intel CorporationInventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhai-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Publication number: 20150155385Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: ApplicationFiled: February 10, 2015Publication date: June 4, 2015Applicant: INTEL CORPORATIONInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Publication number: 20150132940Abstract: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.Type: ApplicationFiled: January 14, 2015Publication date: May 14, 2015Applicant: INTEL CORPORATIONInventors: Madhav Datta, Dave Emory, Subhash M. Joshi, Susanne Menezes, Doowon Suh
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Patent number: 8981435Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.Type: GrantFiled: October 1, 2011Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
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Publication number: 20150069473Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Inventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Michael L. Hattendorf, Subhash M. Joshi
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Patent number: 8952550Abstract: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.Type: GrantFiled: January 12, 2010Date of Patent: February 10, 2015Assignee: Intel CorporationInventors: Madhav Datta, Dave Emory, Subhash M. Joshi, Susanne Menezes, Doowon Suh
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Publication number: 20140339646Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the doping of fins within non-planar transistors, wherein a conformal blocking material layer, such as a dielectric material, may be used to achieve a substantially uniform doping throughout the non-planar transistor fins.Type: ApplicationFiled: September 30, 2011Publication date: November 20, 2014Inventors: Subhash M. Joshi, Michael Hattendorf
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Publication number: 20140151817Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhai-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
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Publication number: 20130264617Abstract: The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.Type: ApplicationFiled: September 30, 2011Publication date: October 10, 2013Inventors: Subhash M. Joshi, Michael Hattendorf