Abstract: Systems and methods for an efficient display data transfer algorithm over a network are disclosed. A compressed frame buffer update transmitted from a server via a network is received by a hardware decompression engine. The hardware decompression engine identifies one or more palette entries indicated in the compressed frame buffer update and determines whether the one or more palette entries is stored in a palette cache of the hardware decompression engine. If the one or more palette entries is not stored in the palette cache, the hardware decompression engine writes the one or more palette entries from an external palette memory to the palette cache. Decompressed display data is generated based on the compressed frame buffer update using the palette cache. The decompressed display data is written to an output buffer of the hardware decompression engine.

Abstract: Systems and methods for an efficient display data transfer algorithm over a network are disclosed. A compressed frame buffer update transmitted from a server via a network is received by a hardware decompression engine. The hardware decompression engine identifies one or more palette entries indicated in the compressed frame buffer update and determines whether the one or more palette entries is stored in a palette cache of the hardware decompression engine. If the one or more palette entries is not stored in the palette cache, the hardware decompression engine writes the one or more palette entries from an external palette memory to the palette cache. Decompressed display data is generated based on the compressed frame buffer update using the palette cache. The decompressed display data is written to an output buffer of the hardware decompression engine.

Abstract: In a digital video processing system for processing full-motion video in computer terminal systems, two main rendering paths are created for a computer terminal system: a screen buffer path and a full-motion video path. The screen buffer path renders a desktop display from a screen buffer within the terminal system. The full-motion video path decodes a video stream and then processes the decoded video stream with a video processing pipeline to fit the video frames within a destination video window within the desktop display. The video processing pipeline performs clipping, blending, chroma resampling, resizing, and color converting of the video frames in pipelined stages with minimal memory accesses. A video adapter then combines the desktop display with the processed digital video for a final terminal display.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: Thin-client terminal systems allow computer systems to be shared by multiple computer users. With modern technology, the cost of implementing a thin-client terminal system can be very low. To improve thin-client terminal systems, a thin-client terminal system accepts user input data in a first serial interface format and transcodes the user input data into a second serial interface format for transmission to a server.

Abstract: In a system and method for a thin-client terminal system having a local screen buffer using a serial bus, a serial bus interface device receives encoded data from a thin-client server system. The serial bus interface device decodes the encoded data according to a serial bus data format and provides the decoded data to a thin-client control system. The thin-client control system distributes the decoded data for processing to a video processing system, an audio processing system, and an input/output control system. The thin-client control system also receives input data from input devices connected to the thin-client terminal system. The input data is processed and encoded according to the serial bus data format for transmission to the thin-client server system.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: A video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, full-motion video may also be displayed in a window defined in the frame buffer. If the native resolution of the full-motion video is larger than the window defined in said frame buffer then valuable memory space and memory bandwidth is being wasted by writing said larger full-motion video in a memory system (and later reading it back) when some data from the full-motion video will be discarded. Thus, a video pre-processor is disclosed to reduce the size of the full-motion video before that full-motion video is written into a memory system. The video pre-processor will scale the full-motion video down to a size no larger than the window defined in the frame buffer.

Abstract: In a digital video processing system for processing full-motion video in computer terminal systems, two main rendering paths are created for a computer terminal system: a screen buffer path and a full-motion video path. The screen buffer path renders a desktop display from a screen buffer within the terminal system. The full-motion video path decodes a video stream and then processes the decoded video stream with a video processing pipeline to fit the video frames within a destination video window within the desktop display. The video processing pipeline performs clipping, blending, chroma resampling, resizing, and color converting of the video frames in pipelined stages with minimal memory accesses. A video adapter then combines the desktop display with the processed digital video for a final terminal display.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: A device and a method of authenticating an electronic device are described. The method may comprise transmitting a token value and a parameter value to the electronic device and selecting a private key within the electronic device using the parameter value. The token value may be processed with a method selected by the parameter value to generate a processed token. The processed token may be compared with an expected processed token and the electronic device may be authenticated if the processed token compares favorably with said expected processed token.

Abstract: A digital video transmission system that operates with three different video rendering paths. A first rendering path operates by receiving display requests and rendering bit-mapped graphics in a local screen buffer. The display information in that local screen buffer is then encoded and transmitted to a remote display system that recreates the content of that local screen buffer in a video buffer of remote display system. A second rendering path operates by receiving encoded video stream requests that can be decoded by the remote display system. Such encoded video streams are sent to the remote display system with minimal addition transport encoding. The third rendering path handles encoded video streams that cannot be handled natively by the remote display system. Such video streams may be either transcoded before transmission or decoded and stored within the local screen buffer.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: A super predictive fetch system and method provides the benefits of a larger word line fill prefetch operation without the penalty normally associated with the larger line fill prefetch operation. Sequential memory access patterns are identified and caused to trigger a fetch of a sequential next line of data. The super predictive fetch operation includes a buffer into which the sequential next line of data is loaded. In one embodiment, the buffer is located in the memory controller. In another embodiment, the buffer is located in the cache controllers.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address insecondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

Abstract: When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.