Patents by Inventor Subramanian Ramesh

Subramanian Ramesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10635408
    Abstract: Prepending a name object or setting a type of a software object to a name and prepending a value object to the software object provides inheritance of a name value pattern by the software object to establish particular types or classes of attributes of the software object without modification of the software object itself that is thus strongly typed and accessible by type.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Faried Abrahams, Vijayaganesh Subramanian, Sandeep Patil Ramesh, Gandhi Sivakumar, Lennox Epstein Thomas
  • Publication number: 20200036384
    Abstract: Systems and methods are provided for detection and compensation of dielectric resonator oscillator frequency drift. DRO frequency drift detection and compensation may be applied in a system, such as an outdoor unit, during handling of received signals. The DRO frequency drift detection and compensation may include, for each input signal, obtaining DRO frequency drift related information, related to the input signal; determining, based on the obtained DRO frequency drift related information, one or more adjustments applicable to processing of the input signal and/or the generation of the output signal using the at least portion of the input signal; and applying the one or more adjustments. The DRO frequency drift detection and compensation may be applied continually, occasionally, and/or periodically.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 30, 2020
    Inventors: Sridhar Ramesh, Subramanian Anantharaman, Harish Maller
  • Patent number: 10432202
    Abstract: Systems and methods are provided for detection and compensation of frequency drifts. Frequency related information may be determined for each of one or more channels in an input signal, and a frequency drift may be determined based on the determined frequency related information of the one or more channels. Frequency related adjustments may be determined based on the frequency drift, and the frequency related adjustments may be applied to different circuits used during one or more of: receiving of the input signal, processing of the input signal, processing of an intermediate signal generated based on the processing of the input signal, and generating of an output signal corresponding to the input signal. Applying the frequency related adjustments may be configured to meet one or more criteria.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: October 1, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Sridhar Ramesh, Subramanian Anantharaman, Harish Maller
  • Patent number: 9465954
    Abstract: Methods and systems for tracking masking of one or more data elements in a datastore are disclosed. The methods involve monitoring one or more masking operations on the one or more data elements in the datastore. Thereafter, one or more metadata associated with the one or more masking operations are identified. Subsequent to identifying the one or more metadata, at least a part of the one or more metadata may be recorded. This metadata may then be transmitted to the destination when a copy (full/partial) of the original data is made, enabling the same information on masking to be obtained at the destination, as at the source.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 11, 2016
    Assignee: DATAGUISE INC.
    Inventors: Malcolm Speedie, Ghanaya Singh, Subramanian Ramesh
  • Patent number: 9268947
    Abstract: The present invention provides a method and system for providing a view of sensitive information across an enterprise. The method includes finding locations of data stores across the enterprise and thereafter searching for sensitive information within the data stores, based on policies. Upon identifying the sensitive information, the sensitive information is optionally quarantined, masked, or encrypted, again based on policies. Information about the locations of the data stores, the sensitive information associated with the data stores, and the masking steps taken, is saved in a repository, and can be tagged. A user may then query the repository to retrieve one or more views of the sensitive information, gaining an overview of the compliance posture of the enterprise relative to one or more data compliance regulations, and for potential data exposure risk areas be able to drill down for actionable level of details.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 23, 2016
    Assignee: Dataguise Inc.
    Inventors: Erik Jarlstrom, Subramanian Ramesh
  • Publication number: 20150026823
    Abstract: A method and system for securing sensitive data content in big data stores is provided. In an example method, entities within the big data store that contain sensitive data are identified. Then, users who have entitlement to access these sensitive entities are identified, along with their level of entitlement. Access controls are then set, based on which users can operate on the sensitive entities. Access or attempts to access these entities is monitored on an ongoing basis. An example system maps entitlement to entities within the big data store that contain sensitive content, to monitor access to these entities and to set access controls for users accessing the big data store.
    Type: Application
    Filed: March 18, 2014
    Publication date: January 22, 2015
    Inventors: Subramanian Ramesh, Jaspaul Singh Chahal, Hemant Diman
  • Publication number: 20150026462
    Abstract: A method and system for access-controlled decryption in big data stores is provided. In an implementation, a system provides a method for encryption that stores meta-information about sensitive data elements being encrypted in a big data store, such as a Hadoop system, in which the bulk of the data may remain unencrypted. In an implementation, the system reads the stored meta-information at decryption time to determine where the encrypted data is within a large and unencrypted file system, and to determine whether or not an individual user has access rights to decrypt a given element of sensitive data. The system allows fine-grain control over access rights to sensitive data during decryption.
    Type: Application
    Filed: June 14, 2014
    Publication date: January 22, 2015
    Inventors: Subramanian Ramesh, Harinder Singh Bedi, Varun Kashyap
  • Publication number: 20140304243
    Abstract: A system groups multiple entities in a large distributed data store (DDS), such as directories and files, into a subset called a domain. The domain is treated as a unit for defining policies to detect and treat sensitive data. Sensitive data can be defined by enterprise or industry. Treatment of sensitive data may include quarantining, masking, and encrypting, of the data or the entity containing the data. Data in a domain can be copied as a unit, with or without the same structure, and with transformations such as masking or encryption, into parts of the same DDS or to a different DDS. Domains can be the unit of access control for organizations, and assigned tags useful for identifying their purpose, ownership, location, or other characteristics. Policies and operations, assigned at the domain level, may vary from domain to domain, but within a domain are uniform, except for specific exclusions.
    Type: Application
    Filed: March 17, 2014
    Publication date: October 9, 2014
    Inventors: Subramanian Ramesh, Jaspaul Singh Chahal
  • Patent number: 8429586
    Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 23, 2013
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl A. Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary S. Delp, Scott A. Peterson
  • Publication number: 20120175683
    Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 12, 2012
    Applicant: LSI Corporation
    Inventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl Anthony Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
  • Patent number: 8178909
    Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 15, 2012
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh
  • Patent number: 8166440
    Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: April 24, 2012
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl Anthony Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
  • Publication number: 20120012896
    Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Inventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh
  • Patent number: 8044437
    Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: October 25, 2011
    Assignee: LSI Logic Corporation
    Inventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh
  • Patent number: 7869251
    Abstract: Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: January 11, 2011
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Ruggero Castagnetti, Subramanian Ramesh
  • Publication number: 20100080035
    Abstract: Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 1, 2010
    Inventors: Ramnath Venkatraman, Ruggero Castagnetti, Subramanian Ramesh
  • Patent number: 7440356
    Abstract: The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: October 21, 2008
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Ruggero Castagnetti, Subramanian Ramesh
  • Patent number: 7404154
    Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: July 22, 2008
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Carl Anthony Monzel, III, Subramanian Ramesh, Robert C. Armstrong, Gary Scott Delp, Scott Allen Peterson
  • Publication number: 20080013383
    Abstract: The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.
    Type: Application
    Filed: July 13, 2006
    Publication date: January 17, 2008
    Inventors: Ramnath Venkatraman, Ruggero Castagnetti, Subramanian Ramesh
  • Patent number: 7114064
    Abstract: A system and method for accessing an Advanced Configuration and Power Interface (ACPI) namespace nodal tree in a computer platform employing an ACPI-compatible implementation is disclosed.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: September 26, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Subramanian Ramesh, Matthew Fischer