Abstract: The present invention provides a method and apparatus for providing dual-port capability to an SRAM array. The internal nodes of two single-port memory cells are connected to each other through metal-layer programming to form a dual-port memory cell. In a preferred embodiment, a split word line design is used for each single-port memory cell, to facilitate dual-port memory access while minimizing the need for IC layout space. An additional benefit of the present invention is that it allows “slices” of a memory array to be converted into dual-port memory, so as to allow both single-port and dual-port memory cells in the same memory array.

Abstract: A system and method for accessing an Advanced Configuration and Power Interface (ACPI) namespace nodal tree in a computer platform employing an ACPI-compatible implementation is disclosed.

Abstract: A system and method for implementing a fast reset of a computer system is described. In one implementation, the fast reset is implemented by adding a new ResetType to the EFIResetSystem( ) function. In particular, a third ResetType, i.e., “EfiResetFast” (FAST option), is added, which is passed as a parameter when calling the EFIResetSystem( ) function. In another implementation, the fast reset is implemented using a new EFI function, referred to herein as “EFIResetFast( )”. In either implementation, in response to a fast reset, the firmware skips several steps typically performed, including some of the core firmware construction, single cell initialization, memory testing, memory re-initialization, and partition creation, and proceeds directly to transfer of control of the platform to a software interface disposed between an OS and firmware.

Abstract: Computer data is transferred from a packed to an unpacked data structure in a computer that enforces aligned memory access and for which the associated compiler lacks a compile-time directive to pack data structures. In an exemplary embodiment, the invention is employed in the pre-processing of Advanced Configuration and Power Interface (ACPI) tables stored in little-endian format for use by a big-endian operating system.

Abstract: A computer pre-processes data collections for use by a big-endian operating system. Pre-processing may include byte swapping, unpacking, bit reversal, or a combination thereof. In one exemplary embodiment, the data collections comprise Advanced Configuration and Power Interface (ACPI) tables.

Abstract: Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned anti-reflective dielectric coatings. The self-alignment allows the size location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less timely, which increases throughput in fabrication.

Abstract: The bits comprising a computer data structure are reversed rapidly and efficiently using a combination of data partitioning and table look ups. In an exemplary embodiment, the invention is employed in the pre-processing of Advanced Configuration and Power Interface (ACPI) tables stored in little-endian format for use by a big-endian operating system.

Abstract: Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned dielectric and a heat sink material. The self-alignment allows the size and location of the break point to be more forgiving of the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication.

Abstract: A wideband CDMA transmission system is disclosed that incorporates transmit diversity in both frequency and space. Some embodiments of the present invention are capable of transmitting a wideband signal with a high data rate to an appropriately-designed wideband CDMA wireless terminal and are also capable of transmitting a narrowband (e.g, IS-95 compliant) signal to a CDMA wireless terminal in the prior art. Some embodiments of the present invention are capable of co-existing in the same frequency spectrum that is allocated to existing narrowband wireless systems. And in some embodiments of the present invention the coded symbols from the interleaver are distributed among multiple carriers that are then radiated by spatially separated antennas.

Abstract: Provided is a method of forming a silicide layer on the top and sidewall surfaces of a polysilicon gate/interconnect in a MOS transistor and on the exposed surfaces of the source and drain regions of the transistor. Devices produced according to the present invention may have different types of silicide formed on their gate and their source/drain electrodes. The invention achieves the advantages of silicide encapsulation of a polysilicon gate in an MOS transistor while also providing silicidation of the source/drain regions of the transistor, thereby reducing electrode resistivity in the transistor and interconnect.

Abstract: A wireless telecommunications system is disclosed that mitigates multipath fading through an improvement in transmit diversity. Furthermore, embodiments of the present invention are well-suited for use with all forward channel multiplexing schemes (e.g., frequency-division multiplexing, time-division multiplexing, code-division multiplexing, etc.) and all modulation techniques (e.g., amplitude modulation, frequency modulation, phase modulation, etc.). An illustrative embodiment of the present invention comprises: a signal inverter for inverting and alternately not-inverting a first signal in accordance with a schedule to create a second signal; a first antenna for transmitting the first signal; and a second antenna for transmitting the second signal.

Abstract: An integrated circuit including a substrate having a memory area and a non-memory area. An embedded memory is fabricated on the substrate within the memory area. First and second semiconductor cells are fabricated on the substrate within the non-memory area. An electromagnetic shield covers substantially memory area. A routing layer is fabricated over the memory and non-memory areas and over the electromagnetic shield. A signal wire is electrically coupled between the first and second semiconductor cells and has a conductive segment which is routed within the routing layer and extends over the memory area.

Abstract: A method is provided for forming thin polysilicon transistor gates using dual doped polysilicon without reducing the ion implant energy. The method comprises depositing polysilicon over a region of a substrate, masking and implanting the polysilicon with dopant impurities to form the channel regions of one conductivity type, and removing the photo resist mask. The polysilicon layer is then masked to define the channel regions of the opposite conductivity type and is implanted with dopant impurities of the opposite conductivity type. Following the dual ion implantation, the photo resist mask is removed and the substrate may be annealed to activate the dopants in the polysilicon. The dual doped polysilicon layer is then polished using a chemical-mechanical polish to achieve a desired thickness for the polysilicon transistor gates. The polysilicon is subsequently masked and etched to define the polysilicon transistor gates.

Abstract: Disclosed are planar DRAM cells including a storage capacitor having a high dielectric constant capacitor dielectric. The DRAM cell also includes an access transistor having a gate dielectric which does not include the high dielectric constant material. A single polysilicon layer is employed to form the gate electrode of the access transistor and a reference plate of the storage capacitor. A disclosed fabrication process forms the high dielectric constant material that is limited to a capacitor region of the DRAM cell and then forms the gate dielectric over an entire active region including both the high dielectric constant material layer at the capacitor region and the semiconductor substrate at the access transistor region. In this manner, a high quality gate dielectric (e.g., silicon oxide) is formed at the access transistor region and a high dielectric constant dielectric layer (e.g., silicon nitride) is formed at the capacitor region.

Abstract: Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithography and an anti-reflective coating. The self-alignment allows the size and location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication.

Abstract: Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.

Abstract: A process is described for forming self-aligned contacts to an MOS device on an integrated circuit structure characterized by the simultaneous formation of the metal silicide gate portion and the metal silicide source/drain portions. The process comprises forming a gate oxide layer on a silicon substrate, forming a polysilicon gate electrode layer over the gate oxide layer, and forming a layer of a first insulation material over the polysilicon gate electrode layer. Metal silicide is simultaneously formed on the exposed surface of the polysilicon gate electrode and over the exposed portions of the silicon substrate. Source/drain regions are formed in the silicon substrate, either before or after formation of the metal silicide over the exposed portions of the silicon substrate, whereby the metal silicide portions on the substrate above the source/drain regions are in electrical communication with the source/drain regions.

Abstract: A defect free monocrystalline layer of silicon on an insulator is produced by forming a thin layer of silicon dioxide on a monocrystalline silicon substrate, forming a thin layer of polycrystalline or amorphous silicon on the silicon dioxide layer and focussing two beams from lamps on the thin silicon layer to form a line image providing a melt zone surrounded by two narrow heated zones having temperatures lower than the melt zone and having a temperature differential of from 2.degree.-10.degree. C./mm decreasing form the melt zone while heating the substrate to a temperature below that of the zones heated by the lamps and scanning the structure.

Abstract: A capped recrystallizable silicon layer covering a substrate is provided with a thin buffer layer between the capping layer and the silicon layer. This recrystallizable silicon layer is then converted to a monocrystalline silicon layer.