Patents by Inventor Su-Chun YANG
Su-Chun YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250062127Abstract: A method of a semiconductor-on-insulator structure includes the following steps. A semiconductor donor substrate is provided. A first implantation process is performed to form an exfoliation layer of the semiconductor donor substrate with a first ion concentration. A second implantation process is performed on a perimeter region of the exfoliation layer to form a high concentration region of the exfoliation layer with a second ion concentration higher than the first ion concentration. The semiconductor donor substrate is bonded to a semiconductor handle substrate, so that the exfoliation layer with the high concentration region is bonded to the semiconductor handle substrate. An annealing process is performed to separate the exfoliation layer from the rest of the semiconductor donor substrate.Type: ApplicationFiled: August 15, 2023Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chun Yang, Jui Hsuan Tsai, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20250053064Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.Type: ApplicationFiled: August 11, 2023Publication date: February 13, 2025Inventors: Su-Chun Yang, Chen Chiang Yu, Jui Hsuan Tsai, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20250031434Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.Type: ApplicationFiled: July 17, 2023Publication date: January 23, 2025Inventors: Yu-Hung Lin, Jih-Churng Twu, Su-Chun Yang, Shih-Peng Tai, Yu-Hao Kuo
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Publication number: 20240379569Abstract: A manufacturing method of a semiconductor device includes the following steps. An electrical insulating and thermal conductive layer is formed over a semiconductor substrate. A dielectric structure is formed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. An opening is formed in the dielectric structure, wherein the opening extending through the dielectric structure and the electrical insulating and thermal conductive layer. A circuit layer is formed in the dielectric structure, wherein the circuit layer fills the opening.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
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Publication number: 20240371818Abstract: A process includes depositing an edge fill dielectric over a first workpiece and a device disposed thereon. The edge fill dielectric is patterned so that only the edge portions remain. A second dielectric material is formed over the first workpiece, device, and edge fill dielectric. A planarization process levels the second dielectric material and the device. A bonding layer is formed thereon and a second workpiece bonded thereto by a dielectric-to-dielectric bond.Type: ApplicationFiled: May 1, 2023Publication date: November 7, 2024Inventors: Su-Chun Yang, Jui Hsuan Tsai, Chiao-Chun Chang, Chu-Chuan Huang, Jih-Churng Twu, Chung-Shi Liu
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Publication number: 20240363586Abstract: A semiconductor package includes a first integrated circuit, a plurality of second integrated circuits, at least one adhesion layer and a molding compound. The second integrated circuits are bonded onto the first integrated circuit. The at least one adhesion layer extends between the second integrated circuits and on sidewalls of the second integrated circuits. The molding compound extends between the second integrated circuits and on the at least one adhesion layer, wherein a surface of the at least one adhesion layer facing away from the first integrated circuit is substantially coplanar with a surface of the molding compound facing away from the first integrated circuit.Type: ApplicationFiled: April 26, 2023Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chun Yang, Jih-Churng Twu, Jui Hsuan Tsai, Chiao-Chun Chang, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 12125794Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer, an etch stop layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The etch stop layer includes silicon nitride and is disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.Type: GrantFiled: February 12, 2023Date of Patent: October 22, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
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Patent number: 12002761Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.Type: GrantFiled: August 10, 2022Date of Patent: June 4, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
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Publication number: 20240128178Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.Type: ApplicationFiled: February 8, 2023Publication date: April 18, 2024Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
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Patent number: 11955378Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.Type: GrantFiled: July 29, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang
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Publication number: 20230369156Abstract: A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.Type: ApplicationFiled: May 16, 2022Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chun Yang, Jih-Churng Twu, Jiung Wu, Chih-Hang Tung, Chen-Hua Yu
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DIE STACKING STRUCTURE, SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE DIE STACKING STRUCTURE
Publication number: 20230360993Abstract: A die stacking structure, a semiconductor package and a method for manufacturing the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; a gap profile modifier, laterally enclosing bottommost portions of the second device dies, wherein a thickness of the gap profile modifier gradually decreases away from sidewalls of the second device dies; and a dielectric material, covering the gap profile modifier and laterally surrounding the second device dies.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chun Yang, Jih-Churng Twu, Jiung Wu, Chih-Hang Tung, Chen-Hua Yu -
Publication number: 20230207473Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer, an etch stop layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The etch stop layer includes silicon nitride and is disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.Type: ApplicationFiled: February 12, 2023Publication date: June 29, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
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Publication number: 20220384352Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
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Publication number: 20220367255Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang
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Patent number: 11456256Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.Type: GrantFiled: May 28, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
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Patent number: 11443981Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.Type: GrantFiled: May 5, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang
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Publication number: 20220285310Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Chen-Hua Yu, Ying-Jui Huang, Chih-Hang Tung, Tung-Liang Shao, Ching-Hua Hsieh, Chien Ling Hwang, Yi-Li Hsiao, Su-Chun Yang
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Patent number: 11342302Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.Type: GrantFiled: February 1, 2019Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ying-Jui Huang, Chih-Hang Tung, Tung-Liang Shao, Ching-Hua Hsieh, Chien Ling Hwang, Yi-Li Hsiao, Su-Chun Yang
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Publication number: 20210375724Abstract: A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Liang SHAO, Wen-Lin SHIH, Su-Chun YANG, Chih-Hang TUNG, Chen-Hua YU