Patents by Inventor Sudarat Lee
Sudarat Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120415Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.Type: ApplicationFiled: October 1, 2022Publication date: April 11, 2024Applicant: Intel CorporationInventors: Scott B. Clendenning, Sudarat Lee, Kevin P. O'Brien, Rachel A. Steinhardt, John J. Plombon, Arnab Sen Gupta, Charles C. Mokhtarzadeh, Gauri Auluck, Tristan A. Tronic, Brandon Holybee, Matthew V. Metz, Dmitri Evgenievich Nikonov, Ian Alexander Young
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Publication number: 20240113220Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Arnab Sen Gupta, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Uygar E. Avci, Kevin P. O'Brien, Scott B. Clendenning, Jason C. Retasket, Shriram Shivaraman, Dominique A. Adams, Carly Rogan, Punyashloka Debashis, Brandon Holybee, Rachel A. Steinhardt, Sudarat Lee
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Patent number: 11935956Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.Type: GrantFiled: June 26, 2020Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Kevin P. O'Brien, Carl Naylor, Chelsey Dorow, Kirby Maxey, Tanay Gosavi, Ashish Verma Penumatcha, Shriram Shivaraman, Chia-Ching Lin, Sudarat Lee, Uygar E. Avci
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Publication number: 20240006481Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a source region, a drain region, a first semiconductor channel between the source region and the drain region, and a second semiconductor channel between the source region and the drain region over the first semiconductor channel. In an embodiment, an insulator is around the source region, the drain region, the first semiconductor channel, and the second semiconductor channel. In an embodiment, a first access hole is in the insulator adjacent to a first edge of the first semiconductor channel, and a second access hole is in the insulator adjacent to a second edge of the first semiconductor channel.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Chelsey DOROW, Kevin P. O'BRIEN, Sudarat LEE, Ande KITAMURA, Ashish Verma PENUMATCHA, Carl H. NAYLOR, Kirby MAXEY, Chia-Ching LIN, Scott B. CLENDENNING, Uygar E. AVCI
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Publication number: 20240008290Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Chia-Ching LIN, Shriram SHIVARAMAN, Kevin P. O'BRIEN, Ashish Verma PENUMATCHA, Chelsey DOROW, Kirby MAXEY, Carl H. NAYLOR, Sudarat LEE, Uygar E. AVCI, Sou-Chi CHANG
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Publication number: 20240006521Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that may be used as access transistors for a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Chia-Ching LIN, Shriram SHIVARAMAN, Kevin P. O'BRIEN, Ashish Verma PENUMATCHA, Chelsey DOROW, Kirby MAXEY, Carl H. NAYLOR, Sudarat LEE, Uygar E. AVCI
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Publication number: 20240006484Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a channel with a first end and a second end opposite from the first end, a first spacer around the first end of the channel, a second spacer around the second end of the channel, and a gate stack over the channel, where the gate stack is between the first spacer and the second spacer. In an embodiment, the transistor may further comprise a first extension contacting the first end of the channel; and a second extension contacting the first end of the channel. In an embodiment, the transistor further comprises conductive layers over the first extension and the second extension outside of the first spacer and the second spacer.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Ashish Verma PENUMATCHA, Kevin P. O'BRIEN, Kirby MAXEY, Carl H. NAYLOR, Chelsey DOROW, Uygar E. AVCI, Matthew V. METZ, Sudarat LEE, Chia-Ching LIN, Sean T. MA
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Publication number: 20230420364Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Kevin P. O'Brien, Tristan A. Tronic, Ande Kitamura, Ashish Verma Penumatcha, Carl Hugo Naylor, Chelsey Dorow, Kirby Maxey, Scott B. Clendenning, Sudarat Lee, Uygar E. Avci
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Publication number: 20230420514Abstract: Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Chelsey DOROW, Sudarat LEE, Kevin P. O'BRIEN, Ande KITAMURA, Ashish Verma PENUMATCHA, Carl H. NAYLOR, Kirby MAXEY, Scott B. CLENDENNING, Uygar E. AVCI, Chia-Ching LIN
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Publication number: 20230420511Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Carl H. NAYLOR, Kirby MAXEY, Kevin P. O'BRIEN, Chelsey DOROW, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Matthew V. METZ, Scott B. CLENDENNING, Chia-Ching LIN, Carly ROGAN, Arnab SEN GUPTA
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Publication number: 20230420510Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Carl H. NAYLOR, Kirby MAXEY, Kevin P. O'BRIEN, Chelsey DOROW, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Matthew V. METZ, Scott B. CLENDENNING, Jiun-Ruey CHEN, Chia-Ching LIN, Carly ROGAN
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Publication number: 20230411390Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: Intel CorporationInventors: Kevin P. O'Brien, Ande Kitamura, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Rachel A. Steinhardt, Scott B. Clendenning, Sudarat Lee, Uygar E. Avci, Chelsey Dorow
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Publication number: 20230411278Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode that includes a bottom region and a pair of vertical regions. First metal layers are outside the vertical regions and in contact with the vertical regions. An insulator is over the first electrode. A second electrode is over the insulator. A second metal layer is on a top surface of the second electrode.Type: ApplicationFiled: March 31, 2023Publication date: December 21, 2023Inventors: Chia-Ching LIN, Sou-Chi CHANG, Kaan OGUZ, Arnab SEN GUPTA, I-Cheng TUNG, Matthew V. METZ, Sudarat LEE, Scott B. CLENDENNING, Uygar E. AVCI, Aaron J. WELSH
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Publication number: 20230411443Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.Type: ApplicationFiled: March 31, 2023Publication date: December 21, 2023Inventors: Kaan OGUZ, Chia-Ching LIN, Arnab SEN GUPTA, I-Cheng TUNG, Sou-Chi CHANG, Sudarat LEE, Matthew V. METZ, Uygar E. AVCI, Scott B. CLENDENNING, Ian A. YOUNG
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Publication number: 20230317783Abstract: Embodiments described herein may be related to forming nano ribbon transistors using layered 2D semiconductor channels. The layered 2D semiconductor channels may be created by forming a scaffold structure that has a first edge that extends from a silicon-based substrate, and a second edge opposite the first edge that is distal to the silicon based substrate. Alternating layers of 2D semiconductor material and a 3D semiconductor material may then be built on the second edge of the scaffold structure. In embodiments, the 3D semiconductor material may then be removed and a gate material deposited around at least a portion of the layers of 2D semiconductor material.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Kirby MAXEY, Carl H. NAYLOR, Uygar E. AVCI, Chelsey DOROW, Kevin P. O'BRIEN, Scott B. CLENDENNING, Matthew V. METZ, Chia-Ching LIN, Sudarat LEE, Ashish Verma PENUMATCHA
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Publication number: 20230253444Abstract: Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.Type: ApplicationFiled: February 8, 2022Publication date: August 10, 2023Applicant: Intel CorporationInventors: Arnab Sen Gupta, Kaan Oguz, Chia-Ching Lin, I-Cheng Tung, Sudarat Lee, Sou-Chi Chang, Matthew V. Metz, Scott B. Clendenning, Uygar E. Avci, Ian A. Young, Jason C. Retasket, Edward O. Johnson, JR.
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Publication number: 20230197728Abstract: An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Nicole K. Thomas, Eric Mattson, Sudarat Lee, Sarah Atanasov, Christopher J. Jezewski, Charles Mokhtarzadeh, Thoe Michaelos, I-Cheng Tung, Charles C. Kuo, Scott B. Clendenning, Matthew V. Metz
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Publication number: 20230197860Abstract: A metal chalcogenide material layer of lower quality provides a transition between a metal chalcogenide material layer of higher quality and a gate insulator material that separates the metal chalcogenide material layers from a gate electrode of a metal-oxide semiconductor field effect transistor (MOSFET) structure. Gate insulator material may be more readily initiated and/or or precisely controlled to a particular thickness when formed on lower quality metal chalcogenide material. Accordingly, such a material stack may be integrated into a variety of transistor structures, including multi-gate, multi-channel nanowire or nanosheet transistor structures.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Carl H. Naylor, Kirby Maxey, Chelsey Dorow, Sudarat Lee, Kevin O'Brien, Ashish V. Penumatcha, Scott B. Clendenning, Uygar Avci, Matthew Metz
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Publication number: 20230113614Abstract: Thin film transistors having CMOS functionality integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first device including a first two-dimensional (2D) material layer, and a first gate stack around the first 2D material layer. The first gate stack has a gate electrode around a gate dielectric layer. A second device is stacked on the first device. The second device includes a second 2D material layer, and a second gate stack around the second 2D material layer. The second gate stack has a gate electrode around a gate dielectric layer. The second 2D material layer has a composition different than a composition of the first 2D material layer.Type: ApplicationFiled: September 24, 2021Publication date: April 13, 2023Inventors: Kevin P. O'BRIEN, Chelsey DOROW, Carl NAYLOR, Kirby MAXEY, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Scott B. CLENDENNING, Urusa ALAAN, Tristan A. TRONIC
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Publication number: 20230098467Abstract: Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Carl H. NAYLOR, Kirby MAXEY, Kevin P. O'BRIEN, Chelsey DOROW, Sudarat LEE, Ashish Verma PENUMATCHA, Shriram SHIVARAMAN, Uygar E. AVCI, Patrick THEOFANIS, Charles MOKHTARZADEH, Matthew V. METZ, Scott B. CLENDENNING