Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a transistor structure that includes a monolayer within an oxide material on a gate metal. There may be a stack of these structures. The monolayer, which may include a semiconductor material, in embodiments may include multiple monolayer sheets that are stacked on top of each other. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, IC structures with an improved two-dimensional (2D) channel architecture. Other embodiments may be disclosed or claimed.

Abstract: Thin film transistors having multi-layer gate dielectric structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is over the 2D material layer, the gate stack having a first side opposite a second side, and the gate stack having a gate electrode around a gate dielectric structure. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack, wherein the first gate spacer and the second gate spacer are continuous with a layer of the gate dielectric structure. A first conductive structure is coupled to the 2D material layer and adjacent to the first gate spacer. A second conductive structure is coupled to the 2D material layer and adjacent to the second gate spacer.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, to IC structures with graphene contacts. Other embodiments may be disclosed or claimed.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a sheet that is a semiconductor. In an embodiment a length dimension of the sheet and a width dimension of the sheet are greater than a thickness dimension of the sheet. In an embodiment, a gate structure is around the sheet, and a first spacer is adjacent to a first end of the gate structure, and a second spacer adjacent to a second end of the gate structure. In an embodiment, a source contact is around the sheet and adjacent to the first spacer, and a drain contact is around the sheet and adjacent to the second spacer.

Abstract: Thin film transistors having strain-inducing structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is on the 2D material layer, the gate stack having a first side opposite a second side. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack. The first gate spacer and the second gate spacer induce a strain on the 2D material layer. A first conductive structure is on the 2D material layer and adjacent to the first gate spacer. A second conductive structure is on the 2D material layer and adjacent to the second gate spacer.

Abstract: Thin film transistors having edge-modulated two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a device layer including a two-dimensional (2D) material layer above a substrate, the 2D material layer including a center portion and first and second edge portions, the center portion consisting essentially of molybdenum or tungsten and of sulfur or selenium, and the first and second edge portions including molybdenum or tungsten and including tellurium.

Abstract: Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.

Abstract: Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

Abstract: A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

Abstract: An integrated circuit (IC) structure having a plurality of backend double-walled capacitors (DWCs) are described. In an example, a first interconnect layer is disposed over a substrate and a second interconnect layer is disposed over the first interconnect layer. In the example, a plurality of DWCs are disposed in the first interconnect layer or the second interconnect layer to provide capacitance to assist the first interconnect layer and the second interconnect layer in providing electrical signal routing and power distribution to one or more devices in the IC structure. In examples, the IC structure includes a logic IC or a coupling substrate.

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

Abstract: Thin film transistors having boron nitride integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first gate stack above a substrate. A 2D channel material layer is above the first gate stack. A second gate stack is above the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack and in contact with the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack and in contact with the 2D channel material layer. A hexagonal boron nitride (hBN) layer is included between the first gate stack and the 2D channel material layer, between the second gate stack and the 2D channel material layer, or both.

Abstract: Thin film transistors having electrostatic double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A 2D channel material layer is on the first gate stack. A second gate stack is on a first portion of the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the 2D channel material layer. A gate electrode of the first gate stack extends beneath a portion of the first conductive contact and beneath a portion of the second conductive contact.

Abstract: Disclosed herein are rare-earth materials, structures, and methods for integrated circuit (IC) structures. For example, in some embodiments, a precursor for atomic layer deposition (ALD) of a rare-earth material in an IC structure may include a rare-earth element and a pincer ligand bonded to the rare-earth element.

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.