Patents by Inventor Sudarshan

Sudarshan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230070765
    Abstract: Systems, methods, and devices for inserting an intraocular lens (IOL) into an eye may be provided. An example haptic optic management system may comprise a first cam assembly comprising a first cam body portion, an opening in the first cam body portion, and haptic folder arms disposed in the opening. The haptic optic management system may further comprise a second cam assembly positioned on one side of the first cam assembly, wherein the second cam assembly comprises a second cam body portion, an opening in the second cam body portion, and optic folders disposed in the opening. The haptic optic management system may further comprise a central plate for holding an intraocular lens in the opening of the second cam body portion, wherein the central plate is disposed between the first cam assembly and the second cam assembly.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 9, 2023
    Inventors: Jack Robert AULD, Matthew Braden FLOWERS, Matthew Douglas MCCAWLEY, Andrew Thomas SCHIEBER, Sudarshan B. SINGH, Marcus Antonio SOUZA
  • Patent number: 11592786
    Abstract: A time-to-digital converter (TDC) includes a count logic and a digital core. The count logic generates a first sequence of counts representing a first sequence of edges of a first periodic signal, and a second sequence of counts representing a second sequence of edges of a second periodic signal. The digital core generates a sequence of outputs representing the phase differences between the first periodic signal and the second periodic signal from the first sequence of counts and the second sequence of counts. Each output is generated from a pair of successive edges of the first direction of one of the periodic signals and an individual one of the other periodic signal occurring between the pair, and the output is set equal to the minimum of difference of the individual one with the first value of the pair and the individual one with the second value of the pair.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 28, 2023
    Assignee: Shaoxing Yuanfang Semiconductor Co., Ltd.
    Inventors: Debasish Behera, Raja Prabhu J, Girisha Angadi Basavaraja, Nandakishore Palla, Manikanta Sakalabhaktula, Chandrashekar Bg, Sudarshan Varadarajan
  • Publication number: 20230057887
    Abstract: A virtual Radio Access Network (vRAN) system (300) for provisioning a virtual Radio Access Network (RAN) that is portable across one or more RAN hardware platforms is provided. The virtual Radio Access Network (vRAN) system (300) includes a waveform development kit (WDK) (302), and a waveform execution environment (304). The waveform development kit (302) defines at least one portable Radio Access Network (RAN) application into a form that is instantiated on a RAN hardware (326). The waveform execution environment (304) (i) monitors real-time schedulable resources in real-time, and (ii) collects one or more statistics and monitors the one or more statistics for network automation. The waveform execution environment (304) includes a RAN hypervisor (314) that virtualizes at least one attribute of a spectral resource required to provision the RAN that is portable across at least one hardware platform of the one or more RAN hardware platforms in the RAN hardware.
    Type: Application
    Filed: May 16, 2021
    Publication date: February 23, 2023
    Inventors: Parag Naik, Saha Anindya, Makarand Kulkami, Hernant Mallapur, Susmit Kumar Datta, Sandeep Pendharkar, Venugopal Kolathur, Sudarshan V
  • Publication number: 20230058318
    Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 23, 2023
    Inventors: Udayakiran Kumar YALLAMARAJU, Xia LI, Pankaj DESHMUKH, Vajram GHANTASALA, Bin YANG, Vishal MISHRA, Bharatheesha Sudarshan JAGIRDAR, Arun Sundaresan IYER, Amod PHADKE, Vanamali BHAT
  • Patent number: 11588755
    Abstract: Information describing changes to a collection of items maintained by a database may be stored in a log file. The information in the log file may be converted into a stream of records describing the changes. The records may be directed to a computing node selected for performing a trigger function in response to the change, based on applying a hash function to a portion of the record, identifying a hash space associated with a value output by the hash function, and mapping from the hash space to the selected computing node.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: February 21, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Parikshit Shivajirao Pol, Subramanian Sankara Subramanian, Rajaprabhu Thiruchi Loganathan, Rama Krishna Sandeep Pokkunuri, Gopinath Duddi, Akshat Vig, Safeer Mohiuddin, Sudarshan Narasimhan
  • Patent number: 11580099
    Abstract: Methods are presented for providing dynamic search filter suggestions that are updated and ranked based on the user filter selections. One method includes detecting a query received in a user interface (UI), calculating, by a search-candidate model, first search results, and calculating, by a suggestions model, first filter suggestions for filter categories to filter responses to the query. The suggestions model is obtained by training a machine-learning algorithm utilizing pairwise learning-to-rank modeling. The first search results and the first filter suggestions are presented in the UI. When a selection in the UI of a filter suggestion is detected, the search-candidate model calculates second search results for the filter categories based on the query and the selected filter suggestion, and the suggestions model calculates second first filter suggestions based on the query and the selected filter suggestion. The second search results and the second filter suggestions are presented in the UI.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 14, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Wenxiang Chen, William Tang, Runfang Zhou, Tanvi Sudarshan Motwani, Jeremy Lwanga, Sara Smoot Gerrard, Daniel Sairom Krishnan Hewlett, Alexandre Patry, Songtao Guo, Sai Krishna Bollam
  • Publication number: 20230044841
    Abstract: An automatic vehicle speed control system for use in a vehicle having an implement is disclosed. The automatic vehicle speed control system includes: a controller configured to: set a speed of the vehicle to a creep setting; monitor one or more operating conditions of the implement; and automatically adjust the speed of the vehicle based on the one or more operating conditions of the implement.
    Type: Application
    Filed: August 3, 2021
    Publication date: February 9, 2023
    Applicant: Caterpillar Inc.
    Inventors: Jeremy KUSHNER, Christopher M. ELLIOTT, Sudarshan A. MAIYUR
  • Patent number: 11568632
    Abstract: This disclosure describes a system for automatically identifying an item from among a variation of items of a same type. For example, an image may be processed and resulting item image information compared with stored item image information to determine a type of item represented in the image. If the matching stored item image information is part of a cluster, the item image information may then be compared with distinctive features associated with stored item image information of the cluster to determine the variation of the item represented in the received image.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 31, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Sudarshan Narasimha Raghavan, Xiaofeng Ren, Michel Leonard Goldstein, Ohil K. Manyam
  • Patent number: 11561945
    Abstract: Systems, methods, and computer products are described herein for identifying data inconsistencies within database tables associated with an application. A master data inconsistency evaluator receives data including at least one selection parameter within at least one database table. By the master data inconsistency evaluator evaluates the at least one selection parameter by comparing the at least one selection parameter with other database tables associated with the application to identify data inconsistencies. The master data inconsistency evaluator repairs the data inconsistencies to further facilitate an error free transaction.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 24, 2023
    Assignee: SAP SE
    Inventors: Shwetha H S, Arindam Bhar, Arun Kumar Gowd, Anand K, Ranjith PR, Jothivenkatesh M, Nabhish Saxena, Bidisha Tripathi, Sudarshan Milind Gokhale, Muskan Gupta
  • Patent number: 11560403
    Abstract: The present invention relates to compounds of formula (I), compositions, methods and uses involving the said formula (I) that inhibit CD47 signaling pathway. The present invention also relates to methods of making such compounds and their uses for the treatment of diseases or disorders mediated by CD47.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: January 24, 2023
    Assignee: AURIGENE ONCOLOGY LIMITED
    Inventors: Pottayil Govindan Nair Sasikumar, Muralidhara Ramachandra, Seetharamaiah Setty Sudarshan Naremaddepalli, Chennakrishnareddy Gundala
  • Patent number: 11550584
    Abstract: Various techniques for accelerating Smith-Waterman sequence alignments are provided. For example, threads in a group of threads are employed to use an interleaved cell layout to store relevant data in registers while computing sub-alignment data for one or more local alignment problems. In another example, specialized instructions that reduce the number of cycles required to compute each sub-alignment score are utilized. In another example, threads are employed to compute sub-alignment data for a subset of columns of one or more local alignment problems while other threads begin computing sub-alignment data based on partial result data received from the preceding threads. After computing a maximum sub-alignment score, a thread stores the maximum sub-alignment score and the corresponding position in global memory.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 10, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Maciej Piotr Tyrlik, Ajay Sudarshan Tirumala, Shirish Gadre
  • Patent number: 11547556
    Abstract: Systems, methods, and devices for inserting an intraocular lens (IOL) into an eye may be provided. An example haptic optic management system may comprise a first cam assembly comprising a first cam body portion, an opening in the first cam body portion, and haptic folder arms disposed in the opening. The haptic optic management system may further comprise a second cam assembly positioned on one side of the first cam assembly, wherein the second cam assembly comprises a second cam body portion, an opening in the second cam body portion, and optic folders disposed in the opening. The haptic optic management system may further comprise a central plate for holding an intraocular lens in the opening of the second cam body portion, wherein the central plate is disposed between the first cam assembly and the second cam assembly.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: January 10, 2023
    Assignee: Alcon Inc.
    Inventors: Jack Robert Auld, Matthew Braden Flowers, Matthew Douglas McCawley, Andrew Thomas Schieber, Sudarshan B. Singh, Marcus Antonio Souza
  • Patent number: 11545575
    Abstract: An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 3, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Man Gu, Wenjun Li, Sudarshan Narayanan
  • Publication number: 20220407483
    Abstract: A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: Sudarshan UDAYASHANKAR, Viola SCHAFFER
  • Publication number: 20220391264
    Abstract: Various embodiments include a parallel processing computer system that enables parallel instances of a program to synchronize at disparate addresses in memory. When the parallel program instances need to exchange data, the program instances synchronize based on a mask that identifies the program instances that are synchronizing. As each program instance reaches the point of synchronization, the program instance blocks and waits for all other program instances to reach the point of synchronization. When all program instances have reached the point of synchronization, at least one program instance executes a synchronous operation to exchange data. The program instances then continue execution at respective and disparate return addresses.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 8, 2022
    Inventors: Ajay Sudarshan TIRUMALA, Olivier GIROUX, Peter NELSON, Gary M. TAROLLI, Ankita UPRETI
  • Patent number: 11521674
    Abstract: A memory access method and a computer system are provided. According to the memory access method, whether to flip the to-be-stored data for storage may be determined based on quantities of “1” and “0” in data to be written into a dynamic random access memory (DRAM) and a storage mode of the DRAM, to reduce a quantity of storage cells with high electric charges in the DRAM, thereby reducing a data error probability.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: December 6, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Kraft Kira, Mathew Deepak, Chirag Sudarshan, Jung Matthias, Weis Christian, Norbert Wehn, Florian Longnos, Gezi Li, Wei Yang
  • Publication number: 20220383937
    Abstract: A memory device comprising a plurality of memory cells situated in a first cell field, multiple first bit lines, each respectively connected to multiple memory cells of the first cell field to enable access to the memory cells via the bit line, and multiple sense amplifier pairs which respectively comprise a first and a second sense amplifier. Each first bit line is assigned to a sense amplifier pair, each first bit line being connected to a respective first semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the first sense amplifier of the sense amplifier pair, to which the bit line is assigned. Each first bit line is connected to a respective second semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the second sense amplifier of the sense amplifier pair, to which the bit line is assigned.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 1, 2022
    Inventors: Andre Guntoro, Chirag Sudarshan, Christian Weis, Leonardo Luiz Ecco, Taha Soliman, Norbert Wehn
  • Publication number: 20220383913
    Abstract: A memory device comprising a cell field having memory cells, N bit lines, which are respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one, N sense amplifiers; a bit shift circuit, which has S switch element rows, S being a whole number greater than one and a row number in the range from zero to S?1 being assignable to each switch element row. Each switch element row includes at least one semiconductor switch element connected to one of the bit lines and one of the sense amplifiers. Switch elements of each row connect all bit lines, whose bit line number is smaller than or equal to N minus the row number, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 1, 2022
    Inventors: Andre Guntoro, Chirag Sudarshan, Christian Weis, Leonardo Luiz Ecco, Taha Soliman, Norbert Wehn
  • Patent number: 11512060
    Abstract: The present invention relates to pharmaceutical compositions of 1,2,4-oxadiazole compounds or a pharmaceutically acceptable salt thereof of formula (I) In the formula Q is O, R1 is the side chain of Ser, R2 is —CO-Thr, R3 is the side chain of Asn or Glu, and R4, R5 and R6 are each H.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: November 29, 2022
    Assignee: Aurigene Discovery Technologies Limited
    Inventors: Pottayil Govindan Nair Sasikumar, Muralidhara Ramachandra, Seetharamaiah Setty Sudarshan Naremaddepalli
  • Patent number: D978223
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: February 14, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Sydney Tye Minnis, Ryan Scott Russell, Martin Aalund, Oszkar Tiberius Bajko, Rahul Gupta, Mona Mayeh, Kristina Perez de Tagle, Sudarshan Rangaraj, Hung-Bing Tan, Arivazhagan Chandrashekaran, Pierre Della Nave