Abstract: A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

Abstract: A phase locked loop design that uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

Abstract: A modulation circuit arranged to modulate a first voltage from a first power supply grid to produce a desired second voltage not greater than the first voltage on a second power supply grid is provided. A digital register is operatively connected to the modulation circuit to determine the desired second voltage on the second power supply grid. Furthermore, the digital register maintains a value representative of an activity level or an anticipated activity level of a circuit connected to the second power supply grid. The modulation circuit maintains the desired second voltage for the circuit connected to the second power supply grid by transferring charge between capacitances.

Abstract: A technique for optimizing decoupling capacitance on an integrated circuit while meeting leakage power constraints of the integrated circuit is provided. The technique involves the formulation of a linear optimization problem using physical characteristics and constraints of the integrated circuit, where a linear solution to the linear optimization problem yields an optimal decoupling capacitance presence on the integrated circuit.

Abstract: A technique that uses active shields to reduce clock skew is provided. The technique uses a shield wire for shielding the signal wire, a driver stage for driving a leading clock signal on the shielding wire, and a signal wire buffer for driving a lagging clock signal on the signal wire, where the leading clock signal is driven onto the first shield wire a phase difference before the lagging clock signal is driven onto the signal wire.

Abstract: An integrated circuit that asymmetrically shields a signal to increase decoupling capacitance is provided. The signal is asymmetrically shielded based on a probability of the signal being at a specific value. Further, a computer system that uses asymmetrically shielding to increase performance is provided. Further, a method for increasing an amount of implicit decoupling capacitance on a circuit through asymmetric shielding is provided. Further, a method to increase component performance by increasing implicit decoupling capacitance is provided.

Abstract: A technique for optimizing decoupling capacitance on an integrated circuit while meeting leakage power constraints of the integrated circuit is provided. The technique involves the formulation of a linear optimization problem using physical characteristics and constraints of the integrated circuit, where a linear solution to the linear optimization problem yields an optimal decoupling capacitance presence on the integrated circuit.

Abstract: A dynamic circuit capable of operating in a normal power consumption mode and at least one reduced power consumption mode is provided. The dynamic circuit is operatively connected to a normal supply voltage and a reduced supply voltage, and is capable of operating at either the normal supply voltage and a normal frequency or at the reduced supply voltage and a reduced frequency. By using such a dynamic circuit, power consumption may be selectively controlled in order to reduce unnecessary power consumption.

Abstract: A technique for reducing the power consumed by a clock driver circuit involves selecting between a first power supply path and a second power supply path in response to a power reduction signal. A driver circuit drives an output clock signal from the selected one of the first power supply path and the second power supply path. By reducing the voltage on one of the first power supply path and the second power supply path, the power consumed by the clock driver circuit may be selectively reduced.

Abstract: A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.

Abstract: A decoupling capacitor assignment technique that increases decoupling capacitance without violating a leakage power constraint of an integrated circuit is provided. The decoupling capacitor assignment technique selectively replaces decoupling capacitors associated with high driver decoupling capacitance need to available decoupling capacitance ratios with thin-oxide decoupling capacitors such that decoupling capacitance is increased and the leakage power constraint is met.

Abstract: An integrated circuit that preferentially shields a signal to increase decoupling capacitance is provided. The signal is preferentially shielded based on a probability of the signal being at a specific value. Further, a method for increasing an amount of decoupling capacitance on a circuit through preferential shielding is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to determine where to route the signal. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by 2using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal.

Abstract: A method and apparatus for optimizing the insertion of decoupling capacitance onto an integrated circuit is provided. Further, a sliding grid based technique for arraying decoupling capacitors into a white-space of an integrated includes sliding a bounded grid across the white-space in order to determine an optimal decap insertion for the white-space. The bounded grid is slid across the white-space in discrete steps. At each discrete step, a potential decap layout is calculated for the region of the white-space that intersects the bounded grid. After a set of potential decap layouts have been calculated for the white-space, the potential decap layout that yields optimal decap insertion is selected, and decap cells are arrayed into the area(s) of the white-space that are demarcated by the selected decap layout.

Abstract: A 120 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 120 degree bump placement structures is provided.

Abstract: A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.

Abstract: A technique for actively shielding a signal such that a signal driver of the signal only participates in discharge events is provided. Because the signal driver only participates in discharge events, the signal driver is non-interacting with respect to other driver devices. Shield wires are set such that an active transition on the signal causes a discharge of capacitance between the signal and the shield wires.

Abstract: A current crowding reduction technique that uses slots positioned between vias and a bump on a metal layer is provided. The presence of slots between the vias and the bump allows current path lengths from the vias to the bump to made substantially equal. Because the current paths have substantially equal current flow among them when the current path lengths are substantially equal, current flows from the vias to the bump in a more uniform manner. Further, a bump and vias structure that uses slots disposed in between vias and a bump is also provided. Further, a method for designing a metal layer having slots positioned in between vias and a bump is also provided.

Abstract: A technique for reducing current crowding on a bump using selective current injection is provided. The technique allows a bump to more uniformly inject current around the bump from vias on a metal layer, where the vias are concentrated on outer regions of the metal layer and have higher via density than that of a central region of vias on the metal layer. Because vias are concentrated on the outer regions of the metal layer, higher current distribution density along current flow paths from the outer regions to the bump compensates for a shorter current path length from the central region to the bump, thus effectively reducing current crowding on the bump. Further, a technique for selectively positioning regions of vias on a metal layer in order to reduce current crowding on a bump is provided.

Abstract: A 180 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 180 degree bump placement structures is provided.