Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to assign a shield potential. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract: A decoupling capacitor assignment technique that increases decoupling capacitance without violating a leakage power constraint of an integrated circuit is provided. The decoupling capacitor assignment technique selectively replaces decoupling capacitors associated with high driver decoupling capacitance need to available decoupling capacitance ratios with thin-oxide decoupling capacitors such that decoupling capacitance is increased and the leakage power constraint is met.

Abstract: An integrated circuit that preferentially shields a signal to increase decoupling capacitance is provided. The signal is preferentially shielded based on a probability of the signal being at a specific value. Further, a method for increasing an amount of decoupling capacitance on a circuit through preferential shielding is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract: A method that preferentially shields a signal to increase decoupling capacitance is provided. The signal is preferentially shielded based on a probability of the signal being at a specific value. Because the shield may also be used to form the power and ground grid, a balanced number of power versus ground lines is desired. A method for inverting the signal to balance the number of power versus ground lines is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to determine where to route the signal. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal.

Abstract: A 180 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 180 degree bump placement structures is provided.

Abstract: A 150 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 150 degree bump placement structures is provided.

Abstract: A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can uniformly flow to and from the bump, effectively leading to reduced current density around the bump. Further, a method for reducing current crowding around a bump using an uniform arrangement of vias around the bump is provided.

Abstract: A 120 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 120 degree bump placement structures is provided.

Abstract: A method and apparatus for post-fabrication adjustment of a phased locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the phased locked loop allows a designer to achieve a desired phase locked loop operating characteristic after fabrication of the adjustable phase locked loop.

Abstract: A phase locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the phase locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the phase locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable phase locked loop behavior.

Abstract: A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can uniformly flow to and from the bump, effectively leading to reduced current density around the bump. Further, a method for reducing current crowding around a bump using an uniform arrangement of vias around the bump is provided.

Abstract: A method and apparatus for assigning decoupling capacitors on an integrated circuit such that leakage power is minimized is provided. Particularly, the method and apparatus use an available capacitance area of an integrated circuit, a capacitance requirement of the integrated circuit, an available thin-oxide capacitance amount, and an available thick-oxide capacitance amount to generate an assignment that indicates what percentage of the available capacitance area should be filled with thin-oxide capacitors and what percentage of the available capacitance area should be filled with thick-oxide capacitors in order to meet the capacitance requirement and minimize leakage power attributable to the thin-oxide and thick-oxide capacitors.

Abstract: A signal shielding technique that assigns voltage potential to shield wires based on the dominant switching direction of a signal is provided. The dominant switching direction is determined based on pre-charge based logic that drives the signal. By determining the voltage potential the signal is more likely to transition to, the shield wires can be implemented so that a discharge event occurs during the dominant transition. Because the signal is more likely to switch in the dominant switching direction, power supply collapses associated with charging events may be reduced.

Abstract: An integrated circuit that asymmetrically shields a signal to increase decoupling capacitance is provided. The signal is asymmetrically shielded based on a probability of the signal being at a specific value. Further, a computer system that uses asymmetrically shielding to increase performance is provided. Further, a method for increasing an amount of implicit decoupling capacitance on a circuit through asymmetric shielding is provided. Further, a method to increase component performance by increasing implicit decoupling capacitance is provided.

Abstract: A transmission gate immune to noise that selectively delivers/draws charge to/from a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided. Further, an NMOS pass gate immune to noise that delivers charge to a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided. Further, a PMOS pass gate immune to noise that draws charge from a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided.

Abstract: A 90 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 90 degree bump placement structures is provided.

Abstract: A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 60 degree bump placement structures is provided.

Abstract: A method for improving integrated circuit by using a patterned bump layout on a layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.