Patents by Inventor Sudhakar Surendran

Sudhakar Surendran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103789
    Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.
    Type: Application
    Filed: December 10, 2024
    Publication date: March 27, 2025
    Inventors: Sudhakar SURENDRAN, Venkatraman RAMAKRISHNAN
  • Patent number: 12197840
    Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: January 14, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Sudhakar Surendran, Venkatraman Ramakrishnan
  • Patent number: 12181974
    Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: December 31, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Veeramanikandan Raju, Sudhakar Surendran, Anand Kumar G
  • Publication number: 20240313749
    Abstract: Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.
    Type: Application
    Filed: December 20, 2023
    Publication date: September 19, 2024
    Inventors: Gregory North, Sudhakar Surendran, Venkatraman Ramakrishnan
  • Publication number: 20240310868
    Abstract: Embodiments disclosed herein relate to managing clock signals across clock domains. In one implementation, a system is configured to derive a base clock signal from a first clock trigger signal produced by a first subsystem in a first clock domain of the clocking system. The system is further configured to generate a second clock trigger signal based on the base clock signal and a main clock of a second subsystem in a second clock domain of the clocking system. The system is also configured to supply the second clock trigger signal to a second peripheral in the second clock domain.
    Type: Application
    Filed: December 28, 2023
    Publication date: September 19, 2024
    Inventors: Gregory North, Sudhakar Surendran, Venkatraman Ramakrishnan
  • Publication number: 20240193337
    Abstract: The present disclosure provides for encoding the signal using a window-based partitioned sequence of literals and then operating over this sequence to determine relevant periodic artifacts. A signal can be received, and then the signal can be abstracted to a sequence of literals. Repeating sub-sequences of literals can be identified in windows of time that increase in width until a repeating sub-sequence is found. Once a repeating sub-sequence is found, the window of time is shifted, and the process repeated. Once the temporal variations of the artifacts are known for the signal, the reference voltage at each of the time periods can be found by resampling the signal in different windows of time, finding temporary reference voltages that are means of samples in each window, determining the reference voltages for each time period, and then determining the DC reference based on a median of the list of reference values.
    Type: Application
    Filed: December 7, 2022
    Publication date: June 13, 2024
    Inventors: Ayan Chakraborty, Sayandeep Sanyal, Pallab Dasgupta, Aritra Hazra, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian, Mohammad Moshiur Rahman
  • Patent number: 11775718
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: October 3, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sudhakar Surendran, Venkatraman Ramakrishnan
  • Publication number: 20230244841
    Abstract: A method includes obtaining, by a computer processor according to computer instructions, data models of intellectual property (IP) cores for hierarchical clock domain crossing (CDC) and reset domain crossing (RDC) verification, where the IP cores include reusable units of logic for a system on a chip (SoC), and performing, by the computer processor based on the data models of the IP cores, the hierarchical CDC and RDC verification for the SoC according to integration of the IP cores in the SoC, where the hierarchical CDC and RDC verification includes consistency verification of functional assumptions with structural analysis of the IP cores individually and in a context of use in the SoC.
    Type: Application
    Filed: January 31, 2022
    Publication date: August 3, 2023
    Inventors: Sudhakar SURENDRAN, Venkatraman RAMAKRISHNAN
  • Publication number: 20230205969
    Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Inventors: Sudhakar SURENDRAN, Venkatraman RAMAKRISHNAN
  • Publication number: 20230176100
    Abstract: Various embodiments disclosed herein provide for a glitch detection and level detection method that use information contained in the signal itself to determine at which resolution or granularity the glitch detection and level detection operates. In particular, the glitch detection method comprises defining a glitch in terms of a change in the area under the waveform which can serve to disambiguate glitches from noises and other transient side effects of level transmissions. Likewise, the level detection method uses an entropy-based metric to identify levels that are significant in context of the entire signal and not in absolute terms.
    Type: Application
    Filed: November 30, 2022
    Publication date: June 8, 2023
    Inventors: Sayandeep Sanyal, Pallab Dasgupta, Aritra Hazra, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian
  • Patent number: 11669668
    Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: June 6, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudhakar Surendran
  • Publication number: 20230110701
    Abstract: A technique for domain crossing verification including receiving a first data object representation of an electrical circuit, performing a domain crossing check on the first data object representation to identify a domain crossing issue, receiving an indication of an assumption for the identified domain crossing issue, converting the first data object representation of the electrical circuit to a second data object representation of the electrical circuit, wherein the second data object representation is synthesized based on the first data object representation, determining one or more verification checks based on the second data object representation and the assumption for the identified domain crossing issue, and performing the one or more verification checks on the second data object representation of the electrical circuit.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 13, 2023
    Inventors: Sudhakar SURENDRAN, Venkatraman RAMAKRISHNAN
  • Publication number: 20230102099
    Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.
    Type: Application
    Filed: December 28, 2021
    Publication date: March 30, 2023
    Inventors: Veeramanikandan RAJU, Sudhakar SURENDRAN, Anand Kumar G
  • Publication number: 20230088503
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.
    Type: Application
    Filed: December 1, 2022
    Publication date: March 23, 2023
    Inventors: Sudhakar Surendran, Venkatraman Ramakrishnan
  • Patent number: 11531798
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: December 20, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Sudhakar Surendran, Venkatraman Ramakrishnan
  • Publication number: 20220269845
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 25, 2022
    Inventors: Sudhakar Surendran, Venkatraman Ramakrishnan
  • Publication number: 20220237355
    Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventor: Sudhakar Surendran
  • Patent number: 11334701
    Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: May 17, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudhakar Surendran
  • Publication number: 20210157967
    Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.
    Type: Application
    Filed: February 5, 2021
    Publication date: May 27, 2021
    Inventor: Sudhakar Surendran
  • Patent number: 10949594
    Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudhakar Surendran