Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: A prefetch scheme in a shared memory multiprocessor disables the prefetch when an address falls within a powered down memory bank. A register stores a bit corresponding to each independently powered memory bank to determine whether that memory bank is prefetchable. When a memory bank is powered down, all bits corresponding to the pages in this row are masked so that they appear as non-prefetchable pages to the prefetch access generation engine preventing an access to any page in this memory bank. A powered down status bit corresponding to the memory bank is used for masking the output of the prefetch enable register. The prefetch enable register is unmodified. This also seamlessly restores the prefetch property of the memory banks when the corresponding memory row is powered up.

Abstract: This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. The hardware power down controller waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.

Abstract: This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down controller informs the master and target specific logic. Further memory accesses are blocked. All pending activities complete. The central controller then proceeds to power down the memory and informs the master and target specific logic upon completion. No requests for wakeup are initiated by master-specific logic from the time a power-down request is received until the completion of power-down.

Abstract: This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.

Abstract: This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down controller informs the master and target specific logic. Further memory accesses are blocked. All pending activities complete. The central controller then proceeds to power down the memory and informs the master and target specific logic upon completion. No requests for wakeup are initiated by master-specific logic from the time a power-down request is received until the completion of power-down.

Abstract: A prefetch scheme in a shared memory multiprocessor disables the prefetch when an address falls within a powered down memory bank. A register stores a bit corresponding to each independently powered memory bank to determine whether that memory bank is prefetchable. When a memory bank is powered down, all bits corresponding to the pages in this row are masked so that they appear as non-prefetchable pages to the prefetch access generation engine preventing an access to any page in this memory bank. A powered down status bit corresponding to the memory bank is used for masking the output of the prefetch enable register. The prefetch enable register is unmodified. This also seamlessly restores the prefetch property of the memory banks when the corresponding memory row is powered up.