Abstract: A single chip integrated circuit 200 is disclosed which includes logic circuitry 202, memory circuitry 204, and a bus 300. First bus control circuitry 302 controls the exchange of signals between logic circuitry 202 and bus 300. Second bus control circuitry 303 controls the exchange of signals between memory circuitry 204 and bus 300. Third bus control circuitry 306 is included which controls the exchange of signals between bus 300 and at least one test pin 206. Mode control circuitry 205 is operable as control circuitry 302, 303, and 306. In the operating mode, mode control circuitry 205 activates first bus control circuitry 302 and second bus control circuitry 303. In a memory test mode, mode control circuitry 205 activates second bus control circuitry 303 and third bus control circuitry 306 and deactivates first bus control circuitry 302.

Abstract: A circuitry is provided for controlling the display of a window on a display operable to display information as at least one field of a plurality of lines of pixels. First counter circuitry is included which is operable to increment with each of a plurality of selected pixels of a given line. First storage circuitry stores position data representing a first coordinate of a reference pixel in the field, the reference pixel being associated with an area of the field in which the window is to be displayed. First adding circuitry is provided which is operable to add a count corresponding to a current pixel and output from the first counter to the position data in the first register. Second counter circuitry is also provided which is operable to increment with each line of the field. Second storage circuitry stores position data representing a second coordinate of the reference pixel.