Patents by Inventor Sudtida Lavangkul
Sudtida Lavangkul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887888Abstract: Methods of forming metal interconnections of an integrated circuit include electroplating two or more metal layers over a metal seed layer, rinsing each of the metal layers with deionized water after the electroplating, and drying each of the metal layers after the rinsing. After forming a last metal layer, the two or more metal layers are annealed thereby forming a final metal layer, resulting in a low defect density of the final metal layer.Type: GrantFiled: June 28, 2021Date of Patent: January 30, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Peter John Holverson, Sudtida Lavangkul
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Publication number: 20230061951Abstract: A method for fabricating a semiconductor product includes forming a dielectric layer over a top level metallization layer of a semiconductor process wafer. The dielectric layer is patterned using a grayscale mask process to define a contact pad opening in the dielectric layer, thereby producing a patterned dielectric layer in which the contact pad opening is aligned to a contact pad defined in the top level metallization layer. A metal layer is deposited over the patterned dielectric layer, including within the contact pad opening. A portion of the metal layer is removed by a chemical mechanical polishing (CMP) process, with a remaining portion of the metal layer having a sloped sidewall.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Sudtida Lavangkul, Yung Shan Chang
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Publication number: 20230017047Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: Ricky Alan Jackson, Erika Lynn Mazotti, Sudtida Lavangkul
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Patent number: 11515266Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.Type: GrantFiled: September 3, 2020Date of Patent: November 29, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ricky Alan Jackson, Erika Lynn Mazotti, Sudtida Lavangkul
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Patent number: 11508721Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.Type: GrantFiled: April 12, 2021Date of Patent: November 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mona M. Eissa, Mark R. Kimmich, Sudtida Lavangkul, Sopa Chevacharoenkul, Mark L. Jenson
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Publication number: 20210327753Abstract: Methods of forming metal interconnections of an integrated circuit include electroplating two or more metal layers over a metal seed layer, rinsing each of the metal layers with deionized water after the electroplating, and drying each of the metal layers after the rinsing. After forming a last metal layer, the two or more metal layers are annealed thereby forming a final metal layer, resulting in a low defect density of the final metal layer.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Peter John Holverson, Sudtida Lavangkul
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Patent number: 11081390Abstract: A method includes electroplate depositing a first metal layer to a first thickness on a metal seed layer, rinsing the first metal layer with deionized water, and after the first rinse process, drying the wafer. The method also includes performing one or more additional electroplating processes that respectively deposit an additional metal layer to a second thickness over the first metal layer, performing an additional rinse process that rinses the additional metal layer with deionized water, and performing an additional drying processes that dries the wafer.Type: GrantFiled: December 31, 2018Date of Patent: August 3, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Peter John Holverson, Sudtida Lavangkul
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Publication number: 20210233903Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Inventors: Mona M. Eissa, Mark R. Kimmich, Sudtida Lavangkul, Sopa Chevacharoenkul, Mark L. Jenson
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Publication number: 20210217706Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.Type: ApplicationFiled: September 3, 2020Publication date: July 15, 2021Inventors: Ricky Alan Jackson, Erika Lynn Mazotti, Sudtida Lavangkul
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Patent number: 10978448Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.Type: GrantFiled: January 22, 2016Date of Patent: April 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mona M. Eissa, Mark R. Kimmich, Sudtida Lavangkul, Sopa Chevacharoenkul, Mark L. Jenson
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Publication number: 20210005560Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.Type: ApplicationFiled: December 9, 2019Publication date: January 7, 2021Applicant: Texas Instruments IncorporatedInventors: Richard Allen Faust, Robert Martin Higgins, Anagha Shashishekhar Kulkarni, Jonathan Philip Davis, Sudtida Lavangkul, Andrew Frank Burnett
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Patent number: 10770406Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.Type: GrantFiled: November 21, 2017Date of Patent: September 8, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ricky Alan Jackson, Erika Lynn Mazotti, Sudtida Lavangkul
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Publication number: 20200211898Abstract: A method includes electroplate depositing a first metal layer to a first thickness on a metal seed layer, rinsing the first metal layer with deionized water, and after the first rinse process, drying the wafer. The method also includes performing one or more additional electroplating processes that respectively deposit an additional metal layer to a second thickness over the first metal layer, performing an additional rinse process that rinses the additional metal layer with deionized water, and performing an additional drying processes that dries the wafer.Type: ApplicationFiled: December 31, 2018Publication date: July 2, 2020Applicant: Texas Instruments IncorporatedInventors: Peter John Holverson, Sudtida Lavangkul
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Publication number: 20190331742Abstract: An integrated fluxgate device includes a substrate that includes a dielectric layer. A fluxgate core is located over the dielectric layer. Lower windings are disposed in a lower metal level between the fluxgate core and the dielectric layer, and upper windings are disposed in an upper metal level above the fluxgate core. A metal structure in the upper metal level or the lower metal level overlaps an end of the fluxgate core and is conductively isolated from the upper and lower windings.Type: ApplicationFiled: July 5, 2019Publication date: October 31, 2019Inventors: Sudtida Lavangkul, Sopa Chevacharoenkul
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Patent number: 10157861Abstract: Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor substrate. A scribe region overlying the semiconductor substrate and a periphery of the integrated circuit includes a crack arrest structure and a scribe seal. The crack arrest structure provides first vertical conductor structure that surrounds the periphery of the integrated circuit. The scribe seal is spaced from and surrounded by the crack arrest structure and provides a second vertical conductor structure. The scribe seal includes first and second vias spaced from each other and connected to one of the conductor layers. The first via is a trench via and the second via is a stitch via, with the second via being located closer to the crack arrest structure than the first via.Type: GrantFiled: July 24, 2017Date of Patent: December 18, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ricky Alan Jackson, Sudtida Lavangkul, Erika Lynn Mazotti
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Patent number: 10147537Abstract: An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.Type: GrantFiled: December 6, 2017Date of Patent: December 4, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dok Won Lee, Sudtida Lavangkul, Erika Lynn Mazotti, William David French
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Patent number: 10005662Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.Type: GrantFiled: August 18, 2017Date of Patent: June 26, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Alan Stringer, Mona Eissa, Byron J. R. Shulver, Sopa Chevacharoenkul, Mark R. Kimmich, Sudtida Lavangkul, Mark L. Jenson
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Publication number: 20180096784Abstract: An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.Type: ApplicationFiled: December 6, 2017Publication date: April 5, 2018Inventors: Dok Won Lee, Sudtida Lavangkul, Erika Lynn Mazotti, William David French
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Publication number: 20180090454Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.Type: ApplicationFiled: November 21, 2017Publication date: March 29, 2018Inventors: Ricky Alan Jackson, Erika Lynn Mazotti, Sudtida Lavangkul
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Patent number: 9870858Abstract: An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.Type: GrantFiled: January 6, 2017Date of Patent: January 16, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dok Won Lee, Sudtida Lavangkul, Erika Lynn Mazotti, William David French