Abstract: Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor substrate. A scribe region overlying the semiconductor substrate and a periphery of the integrated circuit includes a crack arrest structure and a scribe seal. The crack arrest structure provides first vertical conductor structure that surrounds the periphery of the integrated circuit. The scribe seal is spaced from and surrounded by the crack arrest structure and provides a second vertical conductor structure. The scribe seal includes first and second vias spaced from each other and connected to one of the conductor layers. The first via is a trench via and the second via is a stitch via, with the second via being located closer to the crack arrest structure than the first via.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

Abstract: An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: An example apparatus includes a plurality of scribe streets arranged in rows and columns on the surface of a semiconductor wafer; and a plurality of integrated circuit dies arranged in rows and columns and spaced apart by the scribe streets. Each integrated circuit die includes plurality of active areas; a plurality of insulator layers overlying the active areas; a plurality of conductor layers interspersed with and separated by ones of the insulator layers; and a passivation layer overlying a top portion of the uppermost one of the conductor layers. A scribe seal in a scribe region surrounds the periphery of the integrated circuit dies, the scribe seal covered by the passivation layer; and a crack arrest structure is located surrounding and spaced from the scribe seal, and including an opening in the passivation layer that extends to and exposes the upper surface of the crack arrest structure. Methods are disclosed.

Abstract: An integrated fluxgate device contains a fluxgate magnetometer sensor with a fluxgate core of a thin film magnetic material. Metal windings are disposed above and below the fluxgate core. The fluxgate core has at least one end with a width of at least 5 microns. The fluxgate magnetometer sensor has a crack-resistant structure at the end of the fluxgate core. The crack-resistant structure includes at least one of a laterally rounded contour of the fluxgate core at the end having corner radii of at least 2 microns, a lower metal end structure in the lower dielectric layer extending under the end of the fluxgate core, or an upper metal end structure in the upper dielectric layer extending over the end of the fluxgate core.

Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.

Abstract: An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.