Patents by Inventor Sug-Woo Jung
Sug-Woo Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120119181Abstract: A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.Type: ApplicationFiled: September 23, 2011Publication date: May 17, 2012Inventors: Gyu-Hwan OH, Shin-Jae Kang, Sug-Woo Jung, Dong-Hyun Im, Chan-Mi Lee
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Publication number: 20110193048Abstract: Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).Type: ApplicationFiled: April 14, 2011Publication date: August 11, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gyu-Hwan Oh, Sug-Woo Jung, Dong-Hyun Im
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Patent number: 7936024Abstract: A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern.Type: GrantFiled: September 4, 2008Date of Patent: May 3, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Patent number: 7833847Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.Type: GrantFiled: July 15, 2009Date of Patent: November 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Patent number: 7687331Abstract: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.Type: GrantFiled: April 24, 2008Date of Patent: March 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Patent number: 7666786Abstract: A semiconductor device is fabricated by forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate, forming source/drain regions on both sides of the gate electrode structure in the silicon substrate, depositing a physical vapor deposition (PVD) cobalt layer on the gate electrode structure using PVD, depositing a chemical vapor deposition (CVD) cobalt layer on the PVD cobalt layer using CVD, annealing the silicon substrate to react the PVD and CVD cobalt layers with polysilicon on an upper surface of the gate electrode structure, stripping at least a portion of the PVD cobalt layer and the CVD cobalt layer that has not reacted, and annealing the silicon substrate after stripping the at least the portion of the PVD cobalt layer and the CVD cobalt layer.Type: GrantFiled: June 1, 2007Date of Patent: February 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-ho Yun, Gil-heyun Choi, Seong-hwee Cheong, Sug-woo Jung, Hyun-su Kim, Woong-hee Sohn
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Patent number: 7662707Abstract: Methods of forming metal silicide layers in a semiconductor device are provided in which a first metal silicide layer may be formed on a substrate, where the first metal silicide layer comprises a plurality of fragments of a metal silicide that are separated by one or more gaps. A conductive material is selectively deposited into at least some of the gaps in the first metal silicide layer in order to electrically connect at least some of the plurality of fragments.Type: GrantFiled: October 11, 2005Date of Patent: February 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sug-Woo Jung, Gil-Heyun Choi, Jong-Ho Yun, Hyun-Su Kim, Eun-Ji Jung
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Publication number: 20090280605Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When farming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.Type: ApplicationFiled: July 15, 2009Publication date: November 12, 2009Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Patent number: 7579225Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.Type: GrantFiled: September 4, 2008Date of Patent: August 25, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Patent number: 7569483Abstract: Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.Type: GrantFiled: August 8, 2005Date of Patent: August 4, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sug-Woo Jung, Gil-Heyun Choi, Jong-Ho Yun, Kwan-Jong Roh, Eun-Ji Jung, Hyun-Su Kim
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Patent number: 7531459Abstract: Methods of forming a metal salicide layer can include forming a metal layer on a substrate and forming a metal silicide layer on the metal layer using a first thermal process at a first temperature. Then a second process is performed, in-situ with the first thermal process, on the metal layer at a second temperature that is less than the first temperature.Type: GrantFiled: June 13, 2006Date of Patent: May 12, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sug-woo Jung, Gil-heyun Choi, Byung-hee Kim, Jong-ho Yun, Hyun-su Kim, Eun-ji Jung
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Publication number: 20090004789Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.Type: ApplicationFiled: September 4, 2008Publication date: January 1, 2009Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Publication number: 20080315312Abstract: A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern.Type: ApplicationFiled: September 4, 2008Publication date: December 25, 2008Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Patent number: 7435634Abstract: A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern.Type: GrantFiled: April 5, 2006Date of Patent: October 14, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Patent number: 7432185Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.Type: GrantFiled: April 4, 2006Date of Patent: October 7, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Publication number: 20080199991Abstract: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.Type: ApplicationFiled: April 24, 2008Publication date: August 21, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Patent number: 7381989Abstract: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.Type: GrantFiled: March 7, 2006Date of Patent: June 3, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Su Kim, Gil-Heyun Choi, Jong-Ho Yun, Sug-Woo Jung, Eun-Ji Jung
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Publication number: 20070224765Abstract: A semiconductor device is fabricated by forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate, forming source/drain regions on both sides of the gate electrode structure in the silicon substrate, depositing a physical vapor deposition (PVD) cobalt layer on the gate electrode structure using PVD, depositing a chemical vapor deposition (CVD) cobalt layer on the PVD cobalt layer using CVD, annealing the silicon substrate to react the PVD and CVD cobalt layers with polysilicon on an upper surface of the gate electrode structure, stripping at least a portion of the PVD cobalt layer and the CVD cobalt layer that has not reacted, and annealing the silicon substrate after stripping the at least the portion of the PVD cobalt layer and the CVD cobalt layer.Type: ApplicationFiled: June 1, 2007Publication date: September 27, 2007Inventors: Jong-ho Yun, Gil-heyun Choi, Seong-hwee Cheong, Sug-woo Jung, Hyun-su Kim, Woong-hee Sohn
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Patent number: 7238612Abstract: A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.Type: GrantFiled: January 27, 2005Date of Patent: July 3, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-ho Yun, Gil-heyun Choi, Seong-hwee Cheong, Sug-woo Jung, Hyun-su Kim, Woong-hee Sohn
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Patent number: 7232756Abstract: Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.Type: GrantFiled: March 30, 2004Date of Patent: June 19, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Kwan-Jong Roh, Min-Chul Sun, Min-Joo Kim, Sug-Woo Jung, Sun-Pil Youn