Abstract: There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS differential amplifier. The device is configured to operate as an inverter when a supply voltage is below a predetermined threshold.

Abstract: A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the first signal, wherein the switch is responsive to the output, and an integrator connected to the first input, wherein the first signal is a voltage developed by the integrator when a current proportional to the absolute temperature is applied thereto. A method for measuring temperature of a device using a comparator and converting the bitstream of the comparator to a digital output is also given. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, a device comprising a differential pair is provided. A self-biased transistor and a component are coupled to the differential pair. At least one of the self-biased transistor and the component supply a current to the differential pair, wherein the component supplies substantially all of the current when the self-biased transistor is operating in a triode state.

Abstract: A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the first signal, wherein the switch is responsive to the output, and an integrator connected to the first input, wherein the first signal is a voltage developed by the integrator when a current proportional to the absolute temperature is applied thereto. A method for measuring temperature of a device using a comparator and converting the bitstream of the comparator to a digital output is also given. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that receives the delayed output signal of the first delay stage, and generates a delayed output signal from the output of the first delay stage. The first delay stage and the second delay stage are coupled a voltage supply. The magnitude of the delay of the second delayed signal is inversely proportional to the magnitude of the supply voltage to substantially the same degree that the delayed output signal of the first delay stage is proportional to the magnitude of the supply voltage.

Abstract: A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, a device comprising a differential pair is provided. A self-biased transistor and a component are coupled to the differential pair. At least one of the self-biased transistor and the component supply a current to the differential pair, wherein the component supplies substantially all of the current when the self-biased transistor is operating in a triode state.

Abstract: There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS differential amplifier. The device is configured to operate as an inverter when a supply voltage is below a predetermined threshold.

Abstract: A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, there is provided a method of manufacturing a device comprising coupling a fixed biased transistor in parallel to a self-biased transistor and configuring the fixed biased transistor and the self-biased transistor to provide a current to a differential amplifier, wherein the fixed biased transistor is configured to provide current to the differential amplifier when the self-biased transistor is operating in a triode or cut-off region.

Abstract: A low voltage CMOS differential amplifier is provided. More specifically, there is provided a device comprising a differential pair coupled to a first tail current transistor and to a component wherein the first tail current transistor is configured to provide a tail current to the differential pair and the component is configured to provide a tail current to the differential pair when the first tail current transistor is operating in a triode region or in a cut-off region.

Abstract: A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, there is provided a method of manufacturing a device comprising coupling a fixed biased transistor in parallel to a self-biased transistor and configuring the fixed biased transistor and the self-biased transistor to provide a current to a differential amplifier, wherein the fixed biased transistor is configured to provide current to the differential amplifier when the self-biased transistor is operating in a triode or cut-off region.

Abstract: The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to be operated at significantly faster clock speeds. The external strobe signal (XDQS) may be used to generate at least two derivative strobe signals therefrom. Instead of the XDQS signal, the derivative strobe signals are then used, in a predetermined order, to clock in or strobe the data to be written into memory cells. The last generated derivative strobe signal may be used to finally transfer the data bits into memory cells. Once the last of the derivative strobe signals is activated, and so long as there are no more data writes pending in the command pipe for the next clock cycle, the rising or falling edge of the last derivative strobe signal can be detected to turn off further generation of the strobe signals prior to any onset of postamble ringing on the XDQS signal.

Abstract: A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the first signal, wherein the switch is responsive to the output, and an integrator connected to the first input, wherein the first signal is a voltage developed by the integrator when a current proportional to the absolute temperature is applied thereto. A method for measuring temperature of a device using a comparator and converting the bitstream of the comparator to a digital output is also given. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A low voltage CMOS differential amplifier is provided. More specifically, there is provided a device comprising a differential pair coupled to a first tail current transistor and to a component wherein the first tail current transistor is configured to provide a tail current to the differential pair and the component is configured to provide a tail current to the differential pair when the first tail current transistor is operating in a triode region or in a cut-off region.

Abstract: The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to be operated at significantly faster clock speeds. The external strobe signal (XDQS) may be used to generate at least two derivative strobe signals therefrom. Instead of the XDQS signal, the derivative strobe signals are then used, in a predetermined order, to clock in or strobe the data to be written into memory cells. The last generated derivative strobe signal may be used to finally transfer the data bits into memory cells. Once the last of the derivative strobe signals is activated, and so long as there are no more data writes pending in the command pipe for the next clock cycle, the rising or falling edge of the last derivative strobe signal can be detected to turn off further generation of the strobe signals prior to any onset of postamble ringing on the XDQS signal.

Abstract: A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is provided. The system has a sense amplifier, a multiplexer, delay elements, and a provision for hardwiring fast and slow circuits during packaging of a memory circuit. The sense amplifier firing path is split into a slow and a fast path and the multiplexer can select either the slow path or fast path. The memory circuit is tested after fabrication to assess whether each memory cell can be identified as slow or fast circuits and accordingly the fast path or slow path is selected by the multiplexer. The path for each memory cell may be then hardwired during packaging by connecting a select input of multiplexer to a VDD signal or a ground signal.