Patents by Inventor Suguru Kawabata

Suguru Kawabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200353919
    Abstract: A target detection device provided in a vehicle includes: a detector detecting at least one target existing in a peripheral region of the vehicle; a detection controller outputting target data on the at least one target selected based on a predetermined criterion among the detected at least one target; a central controller controlling the vehicle based on the output target data; a storage storing divided region information representing divided regions generated by preliminarily dividing the peripheral region; and a drive assist controller performing control to assist driving of the vehicle. The detection controller selects at least one first target detected in one or more first divided regions of the divided regions set according to an operation state of the drive assist controller, in preference to at least one second target detected in a second divided region other than the one or more first divided regions.
    Type: Application
    Filed: November 16, 2018
    Publication date: November 12, 2020
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Suguru KAWABATA, Takahito IKENOUCHI, Kanichi KOYAMA, Takayuki MORITANI
  • Publication number: 20200065581
    Abstract: The image processing method includes a luminance value information obtaining step of obtaining effective radiance values from a subject, and an image generating step of generating a picture image as a set of unit regions each of which has a luminance value obtained by at least partially removing a regular reflection light component on a surface of the subject from the effective radiance values.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Suguru KAWABATA, Takashi NAKANO, Kazuhiro NATSUAKI, Takahiro TAKIMOTO, Shinobu YAMAZAKI, Daisuke HONDA, Yukio TAMAI
  • Patent number: 10521660
    Abstract: The image processing method includes a luminance value information obtaining step of obtaining effective radiance values from a subject, and an image generating step of generating a picture image as a set of unit regions each of which has a luminance value obtained by at least partially removing a regular reflection light component on a surface of the subject from the effective radiance values.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 31, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Suguru Kawabata, Takashi Nakano, Kazuhiro Natsuaki, Takahiro Takimoto, Shinobu Yamazaki, Daisuke Honda, Yukio Tamai
  • Patent number: 10481313
    Abstract: An image capturing apparatus that includes a polarizing filter of a slit type in which polarization characteristics are improved is realized. A polarizing unit (10) of an image capturing apparatus (100) includes a first polarizer layer (120a) and a second polarizer layer (120b) that hold a dielectric layer (14) therebetween, and a plurality of slits (13) that are arranged at regular intervals in a predetermined direction are formed in each of the first polarizer layer (120a) and the second polarizer layer (120b). A forming material of each of the first polarizer layer (120a) and the second polarizer layer (120b) and a forming material of a wiring layer that controls an operation of a light receiving unit (11) are selected from Al, Si, Cu, Au, Ag, Pt, W, Ti, Sn, In, Ga, Zn, and a compound or alloy that contains at least one of the foregoing.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: November 19, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Daisuke Honda, Takashi Nakano, Suguru Kawabata, Takahiro Takimoto, Kazuhiro Natsuaki, Masayo Uchida, Masaaki Uchihashi
  • Publication number: 20190162890
    Abstract: An image capturing apparatus that includes a polarizing filter of a slit type in which polarization characteristics are improved is realized. A polarizing unit (10) of an image capturing apparatus (100) includes a first polarizer layer (120a) and a second polarizer layer (120b) that hold a dielectric layer (14) therebetween, and a plurality of slits (13) that are arranged at regular intervals in a predetermined direction are formed in each of the first polarizer layer (120a) and the second polarizer layer (120b). A forming material of each of the first polarizer layer (120a) and the second polarizer layer (120b) and a forming material of a wiring layer that controls an operation of a light receiving unit (11) are selected from Al, Si, Cu, Au, Ag, Pt, W, Ti, Sn, In, Ga, Zn, and a compound or alloy that contains at least one of the foregoing.
    Type: Application
    Filed: March 8, 2017
    Publication date: May 30, 2019
    Inventors: DAISUKE HONDA, TAKASHI NAKANO, SUGURU KAWABATA, TAKAHIRO TAKIMOTO, KAZUHIRO NATSUAKI, MASAYO UCHIDA, MASAAKI UCHIHASHI
  • Publication number: 20180090006
    Abstract: An automotive target-detection system includes: sensor units each provided on a vehicle; and a central control unit connected to the sensor units. Each of the sensor units includes: a sensor detecting a target around the vehicle; and a controller generating target information on the detected target, and transmitting it to the central control unit. The controller (i) determines in which one of areas, into which a region around the vehicle is divided, each of targets detected by the sensor is present, (ii) calculates a priority of the targets based on a score set for the areas, (iii) transmits the target information on a target with high priority, (iv) avoids transmitting the target information on a target with low priority, and (v) changes the score of the areas depending on a driving condition.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 29, 2018
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Takahito IKENOUCHI, Kanichi KOYAMA, Suguru KAWABATA
  • Publication number: 20180090008
    Abstract: An automotive target-detection system includes: a sensor unit provided on a vehicle; and a central control unit connected to the sensor unit via an in-car bus. The sensor unit includes: a sensor detecting a target around the vehicle; and a sensor controller generating target information on the detected target, and transmitting it to the central control unit. The sensor controller (i) determines in which one of areas, into which the region around the vehicle is divided, each of the targets is present, (ii) calculates a priority of each of the targets based on a score set for the areas, (iii) transmits the target information on a target whose priority is high, and (iv) avoids transmitting the target information on an other target whose priority is low.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 29, 2018
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Takahito IKENOUCHI, Kanichi KOYAMA, Suguru KAWABATA
  • Publication number: 20170316266
    Abstract: The image processing method includes a luminance value information obtaining step of obtaining effective radiance values from a subject, and an image generating step of generating a picture image as a set of unit regions each of which has a luminance value obtained by at least partially removing a regular reflection light component on a surface of the subject from the effective radiance values.
    Type: Application
    Filed: April 24, 2017
    Publication date: November 2, 2017
    Inventors: Suguru KAWABATA, Takashi NAKANO, Kazuhiro NATSUAKI, Takahiro TAKIMOTO, Shinobu YAMAZAKI, Daisuke HONDA, Yukio TAMAI
  • Publication number: 20170146707
    Abstract: A spectral device includes a polarizing filter and an optical filter. The polarizing filter transmits part of light incident on the polarizing filter, the part of light having a particular polarization component. Light that is incident on and passes through the polarizing filter is converted into linearly polarized light. Light that has passed through the polarizing filter is incident on the optical filter. The optical filter transmits light within a particular frequency range. The optical filter includes a metal layer and a dielectric layer. The dielectric layer is disposed on the metal layer. Multiple slits are formed in the metal layer. The multiple slits are arranged at equal intervals in a predetermined direction. The multiple slits extend in a direction perpendicular to a direction in which the light that has passed through the polarizing filter is polarized.
    Type: Application
    Filed: November 2, 2016
    Publication date: May 25, 2017
    Inventors: Suguru KAWABATA, Takashi NAKANO, Kazuhiro NATSUAKI, Masaaki UCHIHASHI, Masayo UCHIDA
  • Publication number: 20160170108
    Abstract: An optical filter is provided. The optical filter includes a plurality of metal layers, and a dielectric body layer disposed between two adjacent metal layers of the plurality of metal layers. Each of the plurality of metal layers is formed with a plurality of slits, and the plurality of slits formed in one of the adjacent metal layers do not overlap with the plurality of slits formed in the other of the adjacent metal layers in a normal direction of the adjacent metal layers.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 16, 2016
    Inventors: Suguru Kawabata, Takashi Nakano, Kazuhiro Natsuaki, Masaaki Uchihashi, Masayo Uchida
  • Publication number: 20150109093
    Abstract: With miniaturization of a variable resistance element, it is becoming difficult to suppress the adverse effect CMP or etching might have on the resistance variable element. There is proposed a variable resistance element comprising an insulation film and a lower electrode equipped with a first portion surrounded by the insulation film and a columnar-shaped second portion protruded upwards from the first portion beyond an upper surface of the insulation film. The variable resistance element also comprises a variable resistance film that covers a preset region of the insulation film, the present region including the lower electrode, and that is electrically connected to at least an upper surface of the second portion of the lower electrode. The variable resistance element further comprises an upper electrode that covers the variable resistance film and that is electrically connected to the variable resistance film.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 23, 2015
    Inventors: Naoya HIGANO, Yukio TAMAI, Suguru KAWABATA
  • Patent number: 8737115
    Abstract: A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element is changed by voltage pulse application from an initial high resistance state just after produced to a variable resistance state where the switching action is performed. The forming process includes a first step of applying a first pulse having a voltage amplitude lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between both electrodes of the variable resistive element, and a second step of applying a second pulse having a voltage amplitude having the same polarity as the first pulse and not lower than the threshold voltage, thereto after the first step.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 27, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinobu Yamazaki, Kazuya Ishihara, Suguru Kawabata
  • Patent number: 8514607
    Abstract: Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: August 20, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mitsuru Nakura, Kazuya Ishihara, Shinobu Yamazaki, Suguru Kawabata
  • Patent number: 8482956
    Abstract: A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: July 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinobu Yamazaki, Yoshiji Ohta, Kazuya Ishihara, Mitsuru Nakura, Suguru Kawabata, Nobuyoshi Awaya
  • Patent number: 8422270
    Abstract: A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: April 16, 2013
    Assignees: Sharp Kabushiki Kaisha, National University Corporation Kanazawa University
    Inventors: Suguru Kawabata, Shinobu Yamazaki, Yoshiji Ohta, Kazuya Ishihara, Nobuyoshi Awaya, Akio Kitagawa, Kazuya Nakayama
  • Patent number: 8411488
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array for storing user data provided by arranging memory cells each having a variable resistive element having a first electrode, a second electrode, and a variable resistor made of a metal oxide sandwiched between the first and second electrodes. The first and second electrodes are formed of a conductive material forming ohmic junction with the variable resistor and a conductive material forming non-ohmic junction with the variable resistor, respectively. The variable resistor changes between two or more different resistance states by applying a voltage between the electrodes. The resistance state after being changed is maintained in a nonvolatile manner. The variable resistive elements of all memory cells in the memory cell array are set to the highest of the two or more different resistance states in an unused state before the memory cell array is used to store the user data.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 2, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Suguru Kawabata, Shinobu Yamazaki, Kazuya Ishihara, Junya Onishi, Nobuyoshi Awaya, Yukio Tamai
  • Patent number: 8411487
    Abstract: Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 2, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mitsuru Nakura, Kazuya Ishihara, Shinobu Yamazaki, Suguru Kawabata
  • Publication number: 20120300532
    Abstract: A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element is changed by voltage pulse application from an initial high resistance state just after produced to a variable resistance state where the switching action is performed. The forming process includes a first step of applying a first pulse having a voltage amplitude lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between both electrodes of the variable resistive element, and a second step of applying a second pulse having a voltage amplitude having the same polarity as the first pulse and not lower than the threshold voltage, thereto after the first step.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 29, 2012
    Inventors: Shinobu Yamazaki, Kazuya Ishihara, Suguru Kawabata
  • Publication number: 20120081946
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array for storing user data provided by arranging memory cells each having a variable resistive element having a first electrode, a second electrode, and a variable resistor made of a metal oxide sandwiched between the first and second electrodes. The first and second electrodes are formed of a conductive material forming ohmic junction with the variable resistor and a conductive material forming non-ohmic junction with the variable resistor, respectively. The variable resistor changes between two or more different resistance states by applying a voltage between the electrodes. The resistance state after being changed is maintained in a nonvolatile manner. The variable resistive elements of all memory cells in the memory cell array are set to the highest of the two or more different resistance states in an unused state before the memory cell array is used to store the user data.
    Type: Application
    Filed: September 15, 2011
    Publication date: April 5, 2012
    Inventors: Suguru KAWABATA, Shinobu YAMAZAKI, Kazuya ISHIHARA, Junya ONISHI, Nobuyoshi AWAYA, Yukio TAMAI
  • Publication number: 20120075911
    Abstract: Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 29, 2012
    Inventors: Mitsuru NAKURA, Kazuya Ishihara, Shinobu Yamazaki, Suguru Kawabata