Abstract: Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.

Abstract: A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.

Abstract: A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

Abstract: A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

Abstract: A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.