Patents by Inventor Sujeet Ayyapureddi

Sujeet Ayyapureddi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12119043
    Abstract: Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: October 15, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Edmund Gieske, Sujeet Ayyapureddi, Yang Lu, Amitava Majumdar
  • Patent number: 12111727
    Abstract: A memory may perform a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit may count errors which are detected, and set a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: October 8, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240321328
    Abstract: Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during a metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240311231
    Abstract: An exemplary host includes a data mapping decoder configured to decode a swizzle mapping signal received from a memory module to provide a data mapping setting, a data input/output circuit configured to receive a plurality of data bits from the memory module via a data bus, and a data adjustment circuit configured to re-arrange an order of the plurality of data bits based on the data mapping setting to provide a plurality of adjusted data bits.
    Type: Application
    Filed: November 30, 2023
    Publication date: September 19, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sujeet Ayyapureddi, Wesley W. Borie, Dennis G. Montierth, Garth N. Grubb, Mow Yiak Goh, Anthony M. Geidl
  • Publication number: 20240312547
    Abstract: Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 19, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240312512
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Sujeet Ayyapureddi, Randall J. Rooney
  • Publication number: 20240312553
    Abstract: Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 19, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240312550
    Abstract: Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 19, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240296095
    Abstract: Apparatuses, systems, and methods for read commands with different levels of error correction code (ECC) capability. A memory receives a first type of read command and reads data with a first level of ECC and receives a second type of read command and reads the data with a second level of ECC. For example, single error correction (SEC) may be used as part of the first type of read command and more errors may be detected/corrected as part of the second type of read command. A controller may read data using the first type of read command and if a signal is received indicating that an error was detected may read the data again using the second type of read command.
    Type: Application
    Filed: February 27, 2024
    Publication date: September 5, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240296096
    Abstract: Apparatuses, systems, and methods for selectable expansion of error correction capability. A memory includes an error correction code (ECC) circuit which generates a default number of parity bits based on written data, and uses those parity bits to correct error(s) in the data. A setting of the memory may specify some number of extra bits of parity. When enabled the ECC circuit may generate parity include the default parity and the extra parity. The default parity is stored in an ECC column plane. The extra parity is stored in the data column planes. When the extra parity is enabled, the ECC circuit may detect/correct more bits of error in the data.
    Type: Application
    Filed: February 27, 2024
    Publication date: September 5, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240289217
    Abstract: Apparatuses, systems, and methods for variable input error correction code (ECC) circuits. Different modes of a memory device may involve different numbers of bits of information (e.g., data and/or metadata) being accessed. An ECC input circuit receives the variable number of bits of information and provides a fixed number of input bits. An ECC engine uses the input bits to generate parity (during a write) or to locate errors (during a read). The number of input bits may be based on a number of inputs of the ECC engine. The ECC input circuit may generate filler bits to add to the bits of information to generate the input bits.
    Type: Application
    Filed: February 16, 2024
    Publication date: August 29, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240289266
    Abstract: Apparatuses, systems, and methods for adjustable write timing. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. When a first setting is enabled, the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other. When disabled, the metadata may be stored in a single location. A second setting may be used to adjust a write delay to account for different timing when the first setting is enabled vs disabled.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 29, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240281327
    Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, both the metadata and the data may be provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 22, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Sujeet Ayyapureddi, Scott E. Smith
  • Publication number: 20240281390
    Abstract: A memory device includes a stack of eight memory dies having an 8N architecture and a stack of four memory dies having a 4N architecture. A first half and a second half of the stack of eight memory dies can each include 32 channels divided equally across the first half of dies and across the second half of dies. Banks of each of the 32 channels on the first half of dies can be associated with respective first pseudo channels. Banks of each of the 32 channels on the second half of dies can be associated with respective second pseudo channels. The stack of four memory dies can include the 32 channels divided equally amongst the dies, and the banks of each of the 32 channels on the stack of four memory dies can be divided equally across the respective first and second pseudo channels.
    Type: Application
    Filed: January 11, 2024
    Publication date: August 22, 2024
    Inventors: Dong Uk Lee, Sujeet Ayyapureddi, Lingming Yang, Tyler J. Gomm
  • Patent number: 12067270
    Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: August 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel, Elliott C. Cooper-Balis, Amitava Majumdar, Robert M. Walker, Danilo Caraccio
  • Publication number: 20240274220
    Abstract: Systems, methods, and apparatuses related to determining a number of access line contacts for an access line in a memory device are described. An apparatus includes a first data plane, a second data plane, and a sub-access line driver (SAD), all coupled to a local access line. A first portion of the local access line between the SAD and the first data plane includes a first number of access line contacts, a second portion of the local access line between the SAD and the second data plane includes a second number of access line contacts, and the first number of access line contacts are determined by data corresponding to a first function of the first data plane and the second number of access line contacts are determined by data corresponding to a second function of the data plane.
    Type: Application
    Filed: November 9, 2023
    Publication date: August 15, 2024
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240273014
    Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.
    Type: Application
    Filed: February 1, 2024
    Publication date: August 15, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240272979
    Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 15, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240274223
    Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.
    Type: Application
    Filed: February 1, 2024
    Publication date: August 15, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20240272984
    Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 15, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi