Abstract: In a method a computer-implemented efficiency analyzer selects operators from an intermediate representation of a dataflow program. The operators are included in a mapping of the operators to hardware of a computing system to execute the dataflow program. Based on the mapping and a description of the hardware, the efficiency analyzer computes an execution metric associated with executing the operators on the hardware. Based on the execution metric and hardware description, the efficiency analyzer determines an inefficiency metric, and based on the inefficiency metric, the efficiency analyzer determines an inefficiency associated with the dataflow program. The computing system to execute the dataflow program can comprise a coarse grain computing system and the hardware can include a reconfigurable processor of the computing system. A computer program product and a computing system to a the dataflow program can implement the method.

Abstract: According to a computing method a compiler determines a recompute node included in a dataflow application and a checkpoint tensor produced by the recompute node. The compiler determines a recompute cost to recompute the checkpoint tensor, and a memory cost to checkpoint the checkpoint tensor in a memory. Based on the recompute cost and/or the memory cost, the compiler determines a solution cost and compares the solution cost to a solution threshold. Based on comparing the solution cost to the solution threshold, the compiler determines a checkpoint solution to execute the dataflow application. The checkpoint solution can comprise recomputing or checkpointing the checkpoint tensor. In some implementations, the compiler can determine a recompute ratio of the recompute cost to the memory cost and can compare the recompute ratio to the solution threshold. A computer program product and a computing system can implement aspects of the method.

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.

Abstract: In a method a compiler performs a trial compilation to a low level (LL) intermediate representation (IR) of a high level (HL) decision to execute a dataflow application on a computing system. The LLIR comprises hardware resources to execute the application based on the HL decision and the compiler determines a trial result based on LL execution metrics associated with the trail compilation. The compiler performs a trial compilation of a second HL decision to a second LLIR and determines a trial result based on LL execution metrics associated with the second trail compilation. The compiler evaluates the trial results and, based on the evaluations, selects one or both of the HL decisions for executing the dataflow application. A computer program product and a computing system can implement the method.

Abstract: A device may pad a first input into a first padded input, read a first set of input tiles from the first padded input in a first input tiling configuration, process the first set of input tiles through a first section of a graph to generate a first set of output tiles in a first target tiling configuration, and pad the first set of output tiles to generate first set of padded output tiles. A device may arrange the first set of padded output tiles into a second input comprising a second set of input tiles, read the second set of input tiles from the second input in a second input tiling configuration, and process the second set of input tiles through a second section of the graph to generate a second set of output tiles in a second target tiling configuration, different than the first target tiling configuration.

Abstract: A device may write a composed input in memory, wherein the composed input is constructed by composing tiles in a first of set of tiles, wherein the tiles in the first of set of tiles have a first tiling configuration. A device may read a second set of tiles from the composed input, wherein tiles in the second set of tiles have a second tiling configuration that is different from the first tiling configuration.

Abstract: A device may cause a first section of a graph to generate a first plurality of tiles of a tensor, the first plurality of tiles having a first size. A device may initialize a memory area having a second size, larger than the first size, to zeros. A device may write the first plurality of tiles in the memory area, such that a zero padding is formed around edges of the first plurality of tiles written to the memory area, wherein a total width of the zero padding is based on a width difference between the second size and the first size. A device may subsequent to writing the first plurality of tiles, retile the combination of the first plurality of tiles and the zero padding, to generate a second plurality of tiles. A device may cause a second section of the graph to process the second plurality of tiles.

Abstract: A data processing system includes memory and reconfigurable processors, operatively coupled to the memory, configured to execute a sequence of subgraphs of a graph. The sequence of subgraphs includes a preceding subgraph and a succeeding subgraph. The data processing system also includes data flow logic, operatively coupled to the reconfigurable processors and the memory, configured to store a tiled output of the preceding subgraph as a composed input in the memory and make available parts of the composed input for processing by the succeeding subgraph.

Abstract: A data processing system receives a graph that includes a sequence of layers and executes graph cuts between a preceding layer in the graph and a succeeding layer in the graph that succeeds the preceding layer. The preceding layer generates a set of tiles on a tile-by-tile basis and the succeeding layer processes a tensor that includes multiple tiles in the set of tiles. Thus the graph is partitioned into a sequence of subgraphs, and a subgraph in the sequence of subgraphs including a sub-sequence of layers in the sequence of layers. One or more configuration files is generated to configure runtime logic to execute the sequence of subgraphs and the one or more configuration files are stored on a computer-readable media.

Abstract: A data processing system includes compile time logic to section a graph into a sequence of sections, including a first section followed by a second section. The compile time logic configured the first section to generate a first output in a first non-overlapping target configuration in response to processing an input in a first overlapping input configuration, and configures the second section to generate a second output in a second non-overlapping target configuration in response to processing the first output in a second overlapping input configuration. The compile time logic also creates a set of computer instructions to execute the first section and the second section on a target processing system.

Abstract: Disclosed is a data processing system that includes a plurality of reconfigurable processors and processor memory. Runtime logic, operatively coupled to the plurality of reconfigurable processors and the processor memory, is configured to configure at least one reconfigurable processor in the plurality of reconfigurable processors with a first subgraph in a sequence of subgraphs of a graph; load an input onto the processor memory; on a tile-by-tile basis, process a first set of input tiles from the input through the first subgraph and generate a first set of intermediate tiles, load the first set of intermediate tiles onto the processor memory, and process the first set of intermediate tiles through the first subgraph and generate a first set of output tiles; and compose output tiles in the first set of output tiles into a first composed input, and load the first composed input onto the processor memory.

Abstract: A method and system to generate a probabilistic prediction of the presence/absence of cancer in longitudinal and current image datasets, and/or multimodal image datasets, and the location of the cancer, is described. The method and system uses an ensemble of deep learning models. The ensemble includes a global model in the form of a 3D convolutional neural network (CNN) extracting features in the datasets indicative of the presence of cancer on a global basis. The ensemble also includes a two-stage prediction model which includes a first stage or detection model which identifies cancer detection candidates (different cropped volumes of 3D data in the a dataset containing candidates which may be cancer) and a second stage or probability model which incorporates the longitudinal datasets (or multimodal images in a multimodal dataset) and the extracted features from the global model and assigns a cancer probability p to each of the cancer detection candidates.

Abstract: A processing graph of an application with a sequence of processing nodes is obtained which processes an input and generates an intermediate representation a further intermediate representation, and an output representation of the input at stages in the sequence of processing nodes. Graph metadata is generated that specifies a non-overlapping target tiling configuration for the output representation, an overlapping tiling configuration for the input, an overlapping tiling configuration for the intermediate representation, and a third tiling configuration for the further intermediate representation. The processing graph is modified based on the graph metadata to conform to the parameters specified by the graph metadata. A set of computer instructions is then created to execute the modified processing graph on a target processing system.

Abstract: Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections including a first section and a second section. The compile time logic is to configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section. The data processing system further includes runtime logic configured with the compile time logic to execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations.

Abstract: A device having a sheath, a medical device, a stylet, a handle and a plunger device. The handle includes portions connected proximal ends of the sheath, the medical device and the stylet and a chamber portion connected to the actuator. The chamber portion includes a volume of space configured to volumetrically connect to at a lumen of the medical device, the sheath or the stylet and a plunger device configured to be slidably received within the chamber portion. The plunger device is able to pneumatically isolate a proximal portion of the volume of space from a distal portion of the volume of space. Proximal movement of the stylet and the plunger device cause a suction effect (i.e., reduced pressure) at the distal end of the sheath, the medical device and/or the stylet.

Abstract: Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

Abstract: Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative input padding that confines padding to an input. The cumulative input padding pads the input into a padded input. The post-padding tiling tiles the padded input into a set of pre-padded input tiles with a same tile size, tiles intermediate representation of the input into a set of intermediate tiles with a same tile size, and tiles output representation of the input into a set of non-overlapping output tiles with a same tile size. Runtime logic is configured with the compile time logic to execute the modified processing graph to execute the application.

Abstract: In a method, in response to an interface a computer-implemented analysis assistant initiates a presentation of inefficiency results, determined an efficiency analyzer based on a mapping of a dataflow program to execute on hardware of a computing system. The assistant receives an inefficiency included among the inefficiency results and composes formatted inefficiency results comprising a presentation format of the inefficiency to assist a developer of the dataflow program to interpret the inefficiency. The analysis assistant outputs the formatted inefficiency results to an interface, which can comprise an interface to output the formatted inefficiency results for use by the developer to improve the dataflow program in association with the inefficiency. In implementations the presentation can comprise an interactive presentation with a developer of the dataflow program. A computer program product and a computing system can implement the method.

Abstract: In a method a computer-implemented efficiency analyzer selects operators from an intermediate representation of a dataflow program. The operators are included in a mapping of the operators to hardware of a computing system to execute the dataflow program. Based on the mapping and a description of the hardware, the efficiency analyzer computes an execution metric associated with executing the operators on the hardware. Based on the execution metric and hardware description, the efficiency analyzer determines an inefficiency metric, and based on the inefficiency metric, the efficiency analyzer determines an inefficiency associated with the dataflow program. The computing system to execute the dataflow program can comprise a coarse grain computing system and the hardware can include a reconfigurable processor of the computing system. A computer program product and a computing system to a the dataflow program can implement the method.

Abstract: Disclosed embodiments include apparatuses, systems, and methods for providing an atraumatic sheath tip. Various disclosed embodiments seek to help reduce or avoid unnecessary tissue damage upon a sheath being extended to convey an elongated instrument for sampling or treatment. In an illustrative embodiment, an apparatus includes a deformable sheath tip configured to be positioned at a distal end of a sheath. The sheath defines therein a lumen configured to convey an elongated instrument. The sheath tip has a base end disposable at the distal end of the sheath and a contact end. The sheath tip has a first column strength along an axis of the sheath tip that is less than a second column strength of the sheath and a first degree of deformability that is greater than a second degree of deformability of the sheath.