Patents by Inventor Sujit Banerjee
Sujit Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230340267Abstract: Engineered wood products and binder compositions for cold-pressed applications are provided. Methods are also provided for formulating binders and producing the engineered wood products. The binder comprises a soy product and an adhesive formulation. The binders are prepared by mixing the soy product with the adhesive formulation prior to application to a lignocellulosic material to form the engineered wood. The present compositions and methods provide enhanced bonding and shorter holding time at decreased cost.Type: ApplicationFiled: April 21, 2023Publication date: October 26, 2023Applicant: AUBURN UNIVERSITYInventors: BRIAN VIA, SUJIT BANERJEE, OSEI A. ASAFU-ADJAYE, ABIODUN O. ALAWODE
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Publication number: 20230115487Abstract: Methods of dewatering viscous materials are provided. The method comprises contacting the viscous material with pressurized carbon dioxide at a temperature and for a time wherein at least a fraction of water is expressed from the viscous material. Then the pressure is released, and the water expressed from the viscous material is removed to yield a dewatered product. Exemplary viscous materials that can be dewatered by the method include black liquor from wood pulping operations, wet lignin, wet super water absorbent polymers and sugar solutions. The pressurized carbon dioxide is present in subcritical or supercritical form. The method provides dewatering at reduced cost.Type: ApplicationFiled: September 28, 2022Publication date: April 13, 2023Applicant: Auburn UniversityInventors: Osei Asafu-Adjaye, Brian Via, Bhima Sastri, Sujit Banerjee
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Patent number: 11315845Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.Type: GrantFiled: August 17, 2020Date of Patent: April 26, 2022Assignee: Monolith Semiconductor, Inc.Inventors: Kevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee
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Patent number: 10910501Abstract: A device may include a P-N diode, formed within a SiC substrate. The device may include an N-type region formed within the SiC substrate, a P-type region, formed in an upper portion of the N-type region; and an implanted N-type layer, the implanted N-type layer being disposed between the P-type region and the N-type region.Type: GrantFiled: September 5, 2018Date of Patent: February 2, 2021Assignee: Monolith Semiconductor, Inc.Inventors: Kevin Matocha, Kiran Chatty, Blake Powell, Sujit Banerjee
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Patent number: 10899039Abstract: Engineered wood products and binder compositions are provided. In preferred embodiments, the engineered wood products include wax. Methods are also provided for formulating binders for wood comprising unmodified soy flour and synthetic adhesives. The soy-based formulations are prepared by mixing unmodified soy flour with the synthetic adhesive prior to application to the wood or by adding them sequentially to the wood. The present invention provides adequate bonding at reduced cost.Type: GrantFiled: March 16, 2017Date of Patent: January 26, 2021Assignee: Auburn UniversityInventors: Brian Via, Sujit Banerjee
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Publication number: 20210005523Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.Type: ApplicationFiled: August 17, 2020Publication date: January 7, 2021Applicant: Monolith Semiconductor Inc.Inventors: Kevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee
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Patent number: 10804175Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.Type: GrantFiled: March 1, 2017Date of Patent: October 13, 2020Assignee: MONOLITH SEMICONDUCTOR, INC.Inventors: Kevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee
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Patent number: 10692999Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.Type: GrantFiled: February 7, 2018Date of Patent: June 23, 2020Assignee: MONOLITH SEMICONDUCTOR INC.Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
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Publication number: 20200075780Abstract: A device may include a P-N diode, formed within a SiC substrate. The device may include an N-type region formed within the SiC substrate, a P-type region, formed in an upper portion of the N-type region; and an implanted N-type layer, the implanted N-type layer being disposed between the P-type region and the N-type region.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Applicant: Monolith Semiconductor Inc.Inventors: Kevin Matocha, Kiran Chatty, Blake Powell, Sujit Banerjee
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Patent number: 10361302Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.Type: GrantFiled: October 25, 2017Date of Patent: July 23, 2019Assignee: Monolith Semiconductor Inc.Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
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Patent number: 10290732Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.Type: GrantFiled: December 18, 2017Date of Patent: May 14, 2019Assignee: Monolith Semiconductor Inc.Inventors: Kevin Matocha, Kiran Chatty, Sujit Banerjee
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Patent number: 10266694Abstract: Methods are provided for formulating binders for wood comprising unmodified soy flour and synthetic adhesives. The soy-based formulations can be in either liquid or solid form and are prepared by mixing unmodified soy flour with the synthetic adhesive prior to application to the wood or by adding them sequentially to the wood. The present invention provides adequate bonding at reduced cost.Type: GrantFiled: March 11, 2016Date of Patent: April 23, 2019Assignee: Auburn UniversityInventors: Brian Via, William G. Hand, Sujit Banerjee
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Patent number: 10062749Abstract: Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.Type: GrantFiled: June 12, 2014Date of Patent: August 28, 2018Assignee: Monolith Semiconductor Inc.Inventors: Kiran Chatty, Kevin Matocha, Sujit Banerjee, Larry Burton Rowland
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Publication number: 20180175188Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.Type: ApplicationFiled: February 7, 2018Publication date: June 21, 2018Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
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Patent number: 9991376Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.Type: GrantFiled: December 11, 2015Date of Patent: June 5, 2018Assignee: Monolith Semiconductor Inc.Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
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Publication number: 20180122933Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.Type: ApplicationFiled: December 18, 2017Publication date: May 3, 2018Inventors: Kevin MATOCHA, Kiran CHATTY, Sujit BANERJEE
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Publication number: 20180047844Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.Type: ApplicationFiled: October 25, 2017Publication date: February 15, 2018Inventors: Sujit BANERJEE, Kevin MATOCHA, Kiran CHATTY
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Patent number: 9876104Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.Type: GrantFiled: January 23, 2017Date of Patent: January 23, 2018Assignee: Monolith Semiconductor Inc.Inventors: Kevin Matocha, Kiran Chatty, Sujit Banerjee
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Patent number: 9853147Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.Type: GrantFiled: December 9, 2015Date of Patent: December 26, 2017Assignee: Monolith Semiconductor Inc.Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
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Publication number: 20170266930Abstract: Engineered wood products and binder compositions are provided. In preferred embodiments, the engineered wood products include wax. Methods are also provided for formulating binders for wood comprising unmodified soy flour and synthetic adhesives. The soy-based formulations are prepared by mixing unmodified soy flour with the synthetic adhesive prior to application to the wood or by adding them sequentially to the wood. The present invention provides adequate bonding at reduced cost.Type: ApplicationFiled: March 16, 2017Publication date: September 21, 2017Inventors: Brian Via, Sujit Banerjee