Patents by Inventor Sujit Banerjee
Sujit Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8512523Abstract: Methods are provided for altering the tack of an adhesive material by contacting the adhesive material with an amount of a cyclodextrin compound effective to reduce the tack of the adhesive material. In a preferred embodiment, the method is for altering the tack of adhesive contaminants in a process fluid, which includes the steps of providing a process fluid in which are dispersed contaminant particles which comprises one or more adhesive materials (such as pitch, pressure sensitive adhesives, hot melts, latexes, binders, and combinations thereof); and adding to the process an amount of a cyclodextrin compound effective to reduce the tack of the adhesive material. The process fluid can be in a process stream in a pulp and paper mill.Type: GrantFiled: February 14, 2006Date of Patent: August 20, 2013Assignee: Georgia Tech Research CorporationInventor: Sujit Banerjee
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Patent number: 8487646Abstract: In a method for reading a programmable anti-fuse block of a high-voltage integrated circuit a first voltage is applied to a first pin of the HVIC, the first voltage being lowered to a second voltage at a first node. Current is shunted from the first node, thereby lowering the second voltage to a third voltage. An isolation circuit block is then activated to couple the third voltage to a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state. A read signal is generated that causes a voltage potential representative of the programmed state of each anti-fuse to be latched into a corresponding latch element.Type: GrantFiled: April 20, 2011Date of Patent: July 16, 2013Assignee: Power Integrations, Inc.Inventors: Sujit Banerjee, Giao Minh Pham
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Patent number: 8426915Abstract: In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.Type: GrantFiled: June 25, 2012Date of Patent: April 23, 2013Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee
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Patent number: 8410551Abstract: In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.Type: GrantFiled: September 9, 2011Date of Patent: April 2, 2013Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee, Martin H. Manley
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Patent number: 8410548Abstract: In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.Type: GrantFiled: August 3, 2012Date of Patent: April 2, 2013Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee
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Patent number: 8399907Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.Type: GrantFiled: September 30, 2011Date of Patent: March 19, 2013Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee
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Patent number: 8395207Abstract: In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.Type: GrantFiled: June 8, 2011Date of Patent: March 12, 2013Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee, Lin Zhu
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Publication number: 20120313140Abstract: In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.Type: ApplicationFiled: August 3, 2012Publication date: December 13, 2012Applicant: POWER INTEGRATIONS, INC.Inventors: Vijay Parthasarathy, Sujit Banerjee
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Publication number: 20120306012Abstract: In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.Type: ApplicationFiled: June 25, 2012Publication date: December 6, 2012Applicant: POWER INTEGRATIONS, INC.Inventors: Vijay Parthasarathy, Sujit Banerjee
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Patent number: 8309331Abstract: The various embodiments of the present invention relate generally to compositions, systems, and methods for altering rates of catalysis. More particularly, the various embodiments of the present invention are directed toward compositions, systems, and methods for enzymatic hydrolysis of polysaccharides, such as cellulose and starch. An aspect of the present invention comprises a method for altering the rate of conversion of a substrate into a product comprising: providing a substrate in a carrier; mixing a reactant and a co-factor with the carrier to form a substantially homogeneous mixture of the reactant, the co-factor, and the substrate in the carrier; and reacting the reactant with the substrate in the presence of the co- factor to convert at least a portion of the substrate into the product, wherein the reaction rate of the reactant with the substrate in the presence of the co-factor is different than the reaction rate of the reactant with the substrate in the absence of the co-factor.Type: GrantFiled: December 18, 2008Date of Patent: November 13, 2012Assignee: Georgia Tech Research CorporationInventors: Sujit Banerjee, John T. Reye
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Patent number: 8305826Abstract: A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates.Type: GrantFiled: May 7, 2010Date of Patent: November 6, 2012Assignee: Power Integrations, Inc.Inventors: Sujit Banerjee, Giao Minh Pham
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Publication number: 20120273885Abstract: In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.Type: ApplicationFiled: June 25, 2012Publication date: November 1, 2012Applicant: POWER INTEGRATIONS, INC.Inventors: Sujit Banerjee, Vijay Parthasarathy
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Patent number: 8247287Abstract: In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.Type: GrantFiled: November 8, 2011Date of Patent: August 21, 2012Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee
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Publication number: 20120199885Abstract: A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.Type: ApplicationFiled: April 23, 2012Publication date: August 9, 2012Applicant: POWER INTEGRATIONS, INC.Inventors: Sujit Banerjee, Martin H. Manley
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Patent number: 8207577Abstract: In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.Type: GrantFiled: September 29, 2009Date of Patent: June 26, 2012Assignee: Power Integrations, Inc.Inventors: Sujit Banerjee, Vijay Parthasarathy
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Patent number: 8207580Abstract: In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.Type: GrantFiled: May 29, 2009Date of Patent: June 26, 2012Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee
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Publication number: 20120146105Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: ApplicationFiled: February 10, 2012Publication date: June 14, 2012Applicant: Power Integrations, Inc.Inventors: Sujit Banerjee, Vijay Parthasarathy
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Patent number: 8164125Abstract: A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.Type: GrantFiled: May 7, 2010Date of Patent: April 24, 2012Assignee: Power Integrations, Inc.Inventors: Sujit Banerjee, Martin H. Manley
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Publication number: 20120068761Abstract: A soft clamp semiconductor device for preventing inadvertent programming of an unselected anti-fuse (AF) element comprises a MOSFET which includes a first well region disposed in a substrate. Source and drain regions are disposed in the first well region, the drain region being electrically coupled to the first capacitive plate of the AF element and the source region being electrically coupled to a second capacitive plate of the AF element. An insulated gate is disposed over a channel area of the first well region that separates the drain and source regions. A gate capacitance of the MOSFET is substantially less than a capacitance of the unselected AF element such that when a programming voltage is applied to the first capacitive plate, a current flows through the MOSFET that charges the second capacitive plate, thereby reducing a voltage build-up across the unselected AF element.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: Power Integrations, Inc.Inventor: Sujit Banerjee
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Publication number: 20120061720Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.Type: ApplicationFiled: September 30, 2011Publication date: March 15, 2012Applicant: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee