Patents by Inventor Suk-ho Choi

Suk-ho Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120068152
    Abstract: A graphene light-emitting device and a method of manufacturing the same are provided. The graphene light-emitting device includes a p-type graphene doped with a p-type dopant; an n-type graphene doped with an n-type dopant; and an active graphene that is disposed between the type graphene and the n-type graphene and emits light, wherein the p-type graphene, the n-type graphene, and the active graphene are horizontally disposed.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 22, 2012
    Applicant: SAMSUNG LED CO., LTD.
    Inventors: Sung-won HWANG, Geun-woo KO, Sung-hyun SIM, Hun-jae CHUNG, Han-kyu SEONG, Cheol-soo SONE, Jin-hyun LEE, Hyung-duk KO, Suk-ho CHOI, Sung KIM
  • Publication number: 20070267679
    Abstract: A memory device includes a gate stack on a substrate. The gate stack is disposed between a source and a drain. The gate stack includes a tunneling film, storage node, and control oxide film. A thickness of the control oxide film is greater than or equal to about 5 nm and less than or equal to about 30 nm. A method of manufacturing a memory device, including a gate stack on a substrate, wherein the gate stack is disposed between a source and a drain, includes: sequentially forming a tunneling film, a first silicon-rich oxide film, and a control oxide film on the substrate, wherein the first silicon-rich oxide film comprises a SiOx film (1.5<x<1.7); converting the first silicon-rich oxide film into a silicon oxide (SiO2) film comprising silicon nano-crystals; and patterning the control oxide film, the silicon oxide film, and the tunneling film to form the gate stack.
    Type: Application
    Filed: March 15, 2007
    Publication date: November 22, 2007
    Inventors: Young-kwan Cha, Suk-ho Choi, Kyu-il Han, Young-soo Park, Sang-jin Park, Yong-min Park
  • Publication number: 20070187730
    Abstract: Example embodiments may provide memory devices having a charge trap layer which includes a hole trap and an electron trap. The memory device may generate a relatively large flat band voltage gap according to an applied bias voltage. Accordingly, a stable multilevel cell may be realized.
    Type: Application
    Filed: December 7, 2006
    Publication date: August 16, 2007
    Inventors: Sang-Jin Park, Young-kwan Cha, Young-soo Park, Jung-hyun Lee, Suk-ho Choi