Abstract: A display device includes a display panel including a display area including a plurality of pixels and a peripheral area disposed adjacent to the display area, and a cover window including a transmissive area corresponding to the display area and a non-transmissive area corresponding to the peripheral area. The cover window includes a base member, a first print layer formed on a first surface of the base member, and a second print layer formed on the first print layer. The second print layer includes an opening exposing the first print layer, the opening is disposed in the non-transmissive area, the first print layer and the second print layer have a same color, and a gloss of the first print layer is greater than a gloss of the second print layer.

Abstract: Disclosed is a glass-based flexible cover window with improved strength and surface hardness comprising a planar portion formed so as to correspond to a planar region of a flexible display and a folding portion formed so as to be connected to the planar portion, the folding portion being formed so as to correspond to a folding region of the flexible display, wherein the flexible cover window includes a flat glass substrate or a glass substrate having an embossed or engraved uneven pattern formed thereat, an adhesive buffer layer formed at a front surface of the glass substrate, a protective film layer formed on the adhesive buffer layer, and a hard coating layer formed on the protective film layer, and the adhesive buffer layer and the protective film layer are alternately stacked at least n times (where n is a natural number equal to or greater than 1).

Abstract: An apparatus for managing power of an electric vehicle and a method thereof are provided. The apparatus determines whether a user participates in a leisure activity based on surrounding information of the electric vehicle, and supplies power when a plug is connected to an outlet provided in the electric vehicle while entering a leisure mode to allow the user to use the outlet during leisure activities. The apparatus includes an information collector that collects surrounding information of the electronic vehicle, and a controller that determines whether a user is performing a leisure activity based on the surrounding information of the electric vehicle collected by the information collector and adjusts power supply based on whether an outlet provided in the electric vehicle is plugged in in a leisure mode indicating that the user is performing a leisure activity.

Abstract: Disclosed is an antibacterial flexible cover window formed using an antibacterial coating composition containing antibacterial nanoparticles dispersed in a resin coating solution. In the antibacterial coating composition, 0.001 to 0.5 parts by weight of the antibacterial nanoparticles are dispersed in 100 parts by weight of the resin coating solution. The antibacterial flexible cover window includes an antibacterial layer that is formed by applying the antibacterial coating composition to a glass substrate. Therefore, the antibacterial flexible cover window exhibits a good and long-lasting antibacterial activity.

Abstract: A display device includes a substrate that includes a display area and a non-display area, a display element layer disposed on the display area of the substrate, an opposing substrate that faces the substrate and the display element layer, a sealing member disposed on the non-display area and that couples the substrate and the opposing substrate, and a filler disposed between the substrate and the opposing substrate. A thickness of the filler varies in the range of 60% to 400% of a thickness of the sealing member.

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

Abstract: Proposed is a CO2-reduction membrane electrode assembly (MEA), which is a novel MEA capable of changing a reaction condition to an alkaline condition from a problematic acidic condition unfavorable to reactions on a cathode side during catalytic reactions using a cation exchange membrane (CEM) as a separator. In addition, the MEA can reduce a hydrogen evolution reaction (HER), which is a side reaction. In addition, a method of manufacturing the MEA, and a CO2-reduction assembly including the MEA are also proposed.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

Abstract: Proposed is a method of manufacturing a flexible cover window containing a flat portion disposed on a flat area of a flexible display and a folding portion formed in connection to the flat portion and disposed on a folding area of the flexible display. The method is characterized by including: preparing a glass substrate; placing the glass substrate onto a carrier substrate; forming a first coating layer on the glass substrate containing the folding portion; forming a second coating layer on the first coating layer; and separating the glass substrate from the carrier substrate.

Abstract: The present invention provides a plasma-resistant ceramic substrate including a bulk of an oxide composition; and a surface layer in which an oxide composition component constituting the bulk was modified to a composition including one or more anions selected from the group consisting of F? and Cl?, wherein the surface layer is a layer in which a raw material containing one or more anions selected from the group consisting of F? and Cl? is vaporized by heating and adsorbed on the surface of the ceramic substrate to be modified to a composition including one or more anions selected from the group consisting of F? and Cl?, and a method of manufacturing the same. According to the present invention, the plasma resistance and durability of the ceramic substrate can be improved at low cost.

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip, an insulating layer surrounding the first and second semiconductor chips on the first redistribution substrate, a second redistribution substrate disposed on the second semiconductor chip and on which the second semiconductor chip is mounted, and a connection terminal disposed at a side of the first and second semiconductor chips and connected to the first and second redistribution substrates. An inactive surface of the second semiconductor chip is in contact with an inactive surface of the first semiconductor chip. At an interface of the first and second semiconductor chips, an upper portion of the first semiconductor chip and a lower portion of the second semiconductor chip constitute one body formed of a same material.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

Abstract: An apparatus for performing liquid treatment for a substrate is provided. The apparatus for performing the liquid treatment for the substrate may include a housing having a treatment space, a substrate support unit to support and rotate the substrate in the treatment space, a liquid feeding unit including a nozzle device including a central exhaust port and multiple first outer exhaust ports, which are provided in a shape of a ring to form a concentric circle with the central exhaust port to feed mutually different treating liquids onto the substrate through respective exhaust ports, and a controller to control the liquid feeding unit.

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

Abstract: Bacillus sp. SDC-U1 strain deposited to Korean Collection for Type Cultures with Accession No. KCTC 14857BP has quorum quenching activity.

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

Abstract: A flexible cable jumper structure and manufacturing method thereof. The flexible cable jumper device of the present disclosure includes a cover layer, a first metal layer stacked on the cover layer and having a circuit pattern formed thereon, a first dielectric layer stacked on the first metal layer, a first adhesive layer applied on the first dielectric layer, a second metal layer stacked on the first dielectric layer to which the first adhesive layer is applied and having a circuit pattern formed thereon, a heat-resistant layer stacked on the second metal layer, and a terminal layer formed in one region of the heat-resistant layer and electrically connected to the first metal layer and the second metal layer.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.