Patents by Inventor Suk Joong Kim
Suk Joong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978846Abstract: A solid electrolyte membrane for a solid-state battery and a battery comprising the same is provided. The battery may comprise lithium metal as a negative electrode active material. The solid electrolyte membrane comprises an inhibiting layer, which is preferably capable of inhibiting growth of lithium dendrite, because it includes an effective amount of a dendrite growth-inhibiting material, which is capable of ionizing lithium deposited in the form of metal. Thus, when lithium metal is used as a negative electrode for a solid-state battery comprising the solid electrolyte membrane, it is possible to delay and/or inhibit growth of lithium dendrite, and thus to effectively prevent an electrical short-circuit caused by dendrite growth.Type: GrantFiled: June 14, 2019Date of Patent: May 7, 2024Assignee: LG ENERGY SOLUTION, LTD.Inventors: Jung-Pil Lee, Sung-Joong Kang, Eun-Bee Kim, Ji-Hoon Ryu, Suk-Woo Lee, Jae-Hyun Lee
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Patent number: 8193088Abstract: A method of forming metal lines of a semiconductor device includes forming an etch stop layer over a semiconductor substrate over which underlying structures are formed, forming an insulating layer over the etch stop layer, etching the etch stop layer and the insulating layer to form trenches through which the underlying structures are exposed, shrinking the insulating layer by using a thermal treatment process in order to widen openings of the trenches, and filling the trenches with a conductive material.Type: GrantFiled: December 23, 2010Date of Patent: June 5, 2012Assignee: Hynix Semiconductor Inc.Inventor: Suk Joong Kim
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Patent number: 8163627Abstract: A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.Type: GrantFiled: December 13, 2007Date of Patent: April 24, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jung Geun Kim, Eun Soo Kim, Seung Hee Hong, Suk Joong Kim
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Publication number: 20120040527Abstract: A method of forming metal lines of a semiconductor device includes forming an etch stop layer over a semiconductor substrate over which underlying structures are formed, forming an insulating layer over the etch stop layer, etching the etch stop layer and the insulating layer to form trenches through which the underlying structures are exposed, shrinking the insulating layer by using a thermal treatment process in order to widen openings of the trenches, and filling the trenches with a conductive material.Type: ApplicationFiled: December 23, 2010Publication date: February 16, 2012Inventor: Suk Joong KIM
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Patent number: 7977205Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.Type: GrantFiled: June 14, 2010Date of Patent: July 12, 2011Assignee: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
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Publication number: 20100304549Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.Type: ApplicationFiled: June 14, 2010Publication date: December 2, 2010Applicant: Hynix Semiconductor Inc.Inventors: Cha Deok DONG, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
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Patent number: 7736991Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.Type: GrantFiled: December 28, 2006Date of Patent: June 15, 2010Assignee: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
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Patent number: 7682904Abstract: The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.Type: GrantFiled: June 2, 2008Date of Patent: March 23, 2010Assignee: Hynix Semiconductor Inc.Inventors: Eun Soo Kim, Jung Geun Kim, Suk Joong Kim
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Patent number: 7682967Abstract: A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the barrier metal layer, and filling the dual damascene pattern with a conductive material to form a metal wire.Type: GrantFiled: May 10, 2007Date of Patent: March 23, 2010Assignee: Hynix Semiconductor Inc.Inventors: Eun Soo Kim, Jung Geun Kim, Suk Joong Kim
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Publication number: 20090029522Abstract: A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material.Type: ApplicationFiled: December 12, 2007Publication date: January 29, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Whee Won Cho, Seung Hee Hong, Suk Joong Kim, Jong Hye Cho
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Patent number: 7482264Abstract: A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.Type: GrantFiled: November 27, 2006Date of Patent: January 27, 2009Assignee: Hynix Semiconductor Inc.Inventors: Cheol Mo Jeong, Seong Hwan Myung, Eun Soo Kim, Suk Joong Kim
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Publication number: 20090023279Abstract: The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.Type: ApplicationFiled: June 2, 2008Publication date: January 22, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Eun Soo Kim, Jung Geun Kim, Suk Joong Kim
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Publication number: 20090004818Abstract: Disclosed herein is a method of fabricating a semiconductor flash memory device, which method avoids and prevents damage to the conductive layer of a floating gate. The disclosed method can prevent a reduction in the charge trap density characteristics and improve the yield of the device.Type: ApplicationFiled: December 14, 2007Publication date: January 1, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Seung Woo Shin, Eun Soo Kim, Suk Joong Kim, Jong Hye Cho
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Publication number: 20090004819Abstract: In one aspect of the inventive method, a tunnel insulating film, a first conductive layer, and an isolation mask pattern are formed over a semiconductor substrate. The first conductive layer and the tunnel insulating film are patterned along the isolation mask pattern. A trench is formed in the semiconductor substrate. The trench is gap filled with a first insulating film. A polishing process is performed in order to expose the first conductive layer. A height of the first insulating film is lowered. The first conductive layer on the first insulating film is gap-filled with a second insulating film.Type: ApplicationFiled: December 24, 2007Publication date: January 1, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Whee Won Cho, Eun Soo Kim, Suk Joong Kim
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Publication number: 20090004817Abstract: A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.Type: ApplicationFiled: December 13, 2007Publication date: January 1, 2009Inventors: Jung Geun Kim, Eun Soo Kim, Seung Hee Hong, Suk Joong Kim
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Publication number: 20080268612Abstract: The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer.Type: ApplicationFiled: December 21, 2007Publication date: October 30, 2008Inventors: Whee Won Cho, Cheol Mo Jeong, Jung Geun Kim, Suk Joong Kim, Jong Hye Cho
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Publication number: 20080268608Abstract: In a method of fabricating a flash memory device, after an isolation trench is formed, a bottom surface and sidewalls of the trench are gap-filled with a HARP film having a favorable step coverage. A wet etch process is performed such that the HARP film remains on the sidewalls of a tunnel dielectric layer, thereby forming a wing spacer. Accordingly, the tunnel dielectric layer can be protected and an interference phenomenon can be reduced because a control gate to be formed subsequently is located between floating gates.Type: ApplicationFiled: December 6, 2007Publication date: October 30, 2008Applicant: Hynix Semiconductor Inc.Inventors: Suk Joong Kim, Whee Won Cho, Jung Geun Kim, Seong Hwan Myung
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Publication number: 20080220605Abstract: The present invention discloses a method of manufacturing a flash memory device comprising the steps of forming a first insulating layer and a first conductive layer on a semiconductor substrate; etching the first conductive layer, the first insulating layer and the semiconductor substrate to form a trench; forming an isolation layer on a region on which the trench is formed; forming a second conductive layer to make the second conductive layer contact with the first conductive layer; and removing the second conductive layer formed on the isolation layer.Type: ApplicationFiled: December 13, 2007Publication date: September 11, 2008Inventors: Jung Gu Lee, Whee Won Cho, Seong Hwan Myung, Suk Joong Kim
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Publication number: 20080160753Abstract: A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the barrier metal layer, and filling the dual damascene pattern with a conductive material to form a metal wire.Type: ApplicationFiled: May 10, 2007Publication date: July 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Eun Soo Kim, Jung Geun Kim, Suk Joong Kim
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Publication number: 20080105983Abstract: A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.Type: ApplicationFiled: November 27, 2006Publication date: May 8, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Cheol Mo Jeong, Seong Hwan Myung, Eun Soo Kim, Suk Joong Kim