Patents by Inventor Suk Joong Kim

Suk Joong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080102579
    Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 1, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Cha Deok Dong, Whee Won Cho, Jung Geun Kim, Cheol Mo Jeong, Suk Joong Kim, Jung Gu Lee
  • Publication number: 20080003823
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming an interlayer insulating layer and an etch-stop nitride layer over a semiconductor substrate, etching the etch-stop nitride layer and the interlayer insulating layer to form contact holes, forming contacts in the contact holes, forming an oxide layer on the entire surface including the contacts, etching the oxide layer using the etch-stop nitride layer as a target, thus forming trenches through which the contacts and the etch-stop nitride layer adjacent to the contacts are exposed, and forming bit lines in the trenches.
    Type: Application
    Filed: December 29, 2006
    Publication date: January 3, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Whee Won Cho, Seung Hee Hong, Suk Joong Kim, Cheol Mo Jeong
  • Publication number: 20070264790
    Abstract: A method of manufacturing semiconductor devices includes forming a trench in a predetermined region of a substrate. A first insulating layer and a second insulating layer are formed on a entire surface so that the trench is gap-filled. The first and second insulating layers are polished until a top surface of the substrate is exposed. A wet etch process of a low selectivity is performed, so that a portion of the first insulating layer remains on sides of the trench while stripping the second insulating layer. A third insulating layer is formed on the entire surface, so that the trench is gap-filled, thereby forming an isolation structure.
    Type: Application
    Filed: November 8, 2006
    Publication date: November 15, 2007
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Whee Won Cho, Jung Geun Kim, Suk Joong Kim