Abstract: A method of manufacturing a heat dissipation adhesive layer for a display device is disclosed that includes providing a liner, a first coating layer on the liner, and a heat dissipation layer on the first coating layer, forming a mask dam surrounding the heat dissipation layer, and forming a second coating layer inside the mask dam.

Abstract: A catalyst electrode for production of 2,5-furandicarboxylic acid according to an embodiment of the present invention includes: a first metal substrate; and a second metal hydroxide coating layer located on a surface of the first metal substrate, wherein the first metal substrate includes one or more micro-sized first metal particles on the surface thereof, and the second metal hydroxide coating layer may be located on a surface of the first metal particles.

Abstract: Equipment for manufacturing a separator plate for a fuel cell comprises: a press which receives a conveyed first metal strip and second metal strip, vertically arranges the metal strips side by side, and forms patterns on each of the first metal strip and the second metal strip; a welding machine which overlaps the first metal strip and the second metal strip conveyed from the press, and integrally joins the metal strips by welding same in a state in which the patterns are aligned face-to-face with each other; and guide rolls which are arranged in front of and behind the press and guide the first metal strip so that the first metal strip is supplied to the welding machine at an overlapping position with the second metal strip after passing through the press at a position spaced vertically apart from the second metal strip.

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

Abstract: A semiconductor memory device includes a bit line extending in a first direction on a substrate, an active pattern on the bit line, a word line on a first sidewall of the active pattern and extending in a second direction, a back gate electrode on a second sidewall of the active pattern and extending in the second direction, a gate isolation pattern on the first sidewall of the active pattern and including a low-k pattern extending in the second direction, and a data storage pattern connected to the second surface of the active pattern. The word line is between the active pattern and the gate isolation pattern, and a vertical distance between the bit line and the word line is greater than a vertical distance between the bit line and the low-k pattern.

Abstract: Disclosed herein is a method of controlling a display driving apparatus configured to operate a display device that displays an image. The method includes receiving a first image signal (RGB) from an external system, converting the first image signal (RGB) into a second image signal (RGB?) in a format processable by a data driver, outputting the second image signal (RGB?), converting the second image signal (RGB?) into a source signal based on a data control signal generated by a timing controller, converting heat energy generated by the data driver into a voltage, calculating a temperature of the data driver based on the converted voltage, and changing a resistance for impedance matching between the timing controller and the data driver based on the calculated temperature.

Abstract: This application relates to an optical sensor element. In one aspect, the optical sensor element includes a graphite column including one or more graphite rods. The optical sensor element may also include one or more first graphene layers partly or entirely covering each of both ends of the graphite column. The optical sensor element may further include one or more second graphene layers partly or entirely covering the outer circumferential surface of the graphite column. This application also relates to an optical sensor for measuring the concentration of a greenhouse gas and the optical sensor includes the optical sensor element.

Abstract: The present invention relates to a method of forming a plasma resistant oxyfluoride coating layer, including: mounting a substrate on a substrate holder provided in a chamber; causing an electron beam scanned from an electron gun to be incident on an oxide evaporation source accommodated in a first crucible, and heating, melting, and vaporizing the oxide evaporation source as the electron beam is incident on the oxide evaporation source; vaporizing a fluoride accommodated in a second crucible; and advancing an evaporation gas generated from the oxide evaporation source and a fluorine-containing gas generated from the fluoride toward the substrate, and reacting the evaporation gas generated from the oxide evaporation source and the fluorine-containing gas generated from the fluoride to deposit an oxyfluoride on the substrate.

Abstract: Provided is an adhesive composition including lysine, alpha ketoglutaric acid, and water, wherein the lysine and the alpha ketoglutaric acid are present in the form of an aqueous salt solution and do not form precipitates in the aqueous solution.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: A semiconductor package includes a substrate, an interposer on the substrate, a semiconductor chip stack on the interposer, a silicon capacitor layer on the interposer, a first semiconductor chip on the silicon capacitor layer, and a molding layer at least partially surrounding side surfaces of the semiconductor chip stack, the silicon capacitor layer and the first semiconductor chip. The semiconductor chip stack and the first semiconductor chip are laterally spaced apart from each other. A top surface of the first semiconductor chip is coplanar with a top surface of the molding layer and a top surface of the semiconductor chip stack.

Abstract: A pixel of a display device may pre-charge a light emitting element in non-emission periods immediately before emission periods by varying a voltage level of an initialization voltage. As a result, a luminance non-uniformity phenomenon that may occur as the result of a deterioration deviation of the light emitting element may be removed or reduced.

Abstract: The present disclosure relates to a manufacturing method of a continuous sheet for circuit board production providing reel type laminates in a roll-to-roll continuous process without a belt press by connecting at least two or more sheet type metal laminates using an adhesion substrate which includes a reinforcement film and a conductor, the manufacturing method providing improved mechanical properties, and excellent chemical resistance and productivity, and the continuous sheet for circuit board production manufactured therefrom.

Abstract: A D2D scheduling method in a UAV-based IoT network includes: (a) acquiring a geographical map for all transmission links of a D2D network within a network coverage area; (b) applying the geographical map to a sparse convolution model to extract a feature map; (c) defining the feature map for a time slot t as a state St, and then inputting the feature map to actor and critic networks of a reinforcement learning-based scheduling policy learning model, respectively, and selecting a scheduling decision At for the D2D transmission link based on a scheduling output of the actor network and a greedy strategy; and (d) transmitting the scheduling decision At to the D2D network and then receiving reward when the scheduling decision At is applied by the D2D network, wherein the reward is calculated as a total achievable transmission rate.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

Abstract: Provided is a substrate processing apparatus. The substrate processing apparatus includes a chamber in which a process with respect to a substrate is performed, a susceptor which is installed in the chamber and on which the substrate is placed, a plurality of lift pins passing through the susceptor to support the substrate, and a plurality of protection plugs protruding from a bottom surface of the susceptor to surround a portion of each of the lift pins protruding from the bottom surface of the susceptor.

Abstract: A semiconductor package includes a substrate, an interposer on the substrate, a semiconductor chip stack on the interposer, a silicon capacitor layer on the interposer, a first semiconductor chip on the silicon capacitor layer, and a molding layer at least partially surrounding side surfaces of the semiconductor chip stack, the silicon capacitor layer and the first semiconductor chip. The semiconductor chip stack and the first semiconductor chip are laterally spaced apart from each other. A top surface of the first semiconductor chip is coplanar with a top surface of the molding layer and a top surface of the semiconductor chip stack.

Abstract: There is provided a semiconductor device in which thickness variation of a substrate is precisely controlled. The semiconductor device includes a substrate comprising cell regions, a dummy region between the cell regions, an upper surface and a lower surface opposite the upper surface in a first direction, an active pattern disposed on the upper surface of the substrate, the active pattern comprising a lower pattern extending in a second direction crossing the first direction and a plurality of sheet patterns spaced apart in the first direction from each other, the plurality of sheet patterns being disposed in the cell region, a source/drain pattern disposed between the gate structures adjacent to each other, and a buried insulating pattern penetrating the substrate and the lower pattern in the dummy region.

Abstract: A semiconductor device includes a substrate with opposite first and second surfaces in a first direction, an active pattern on the first surface in a second direction, a gate electrode in a third direction on the active pattern, a source/drain on at least one side of the gate electrode and connected to the active pattern, a gate cutting structure on one side of the active pattern and cutting the gate electrode, the gate cutting structure including third and fourth surfaces opposite to each other in the first direction, and the fourth surface being coplanar with the second surface of the substrate, a power rail on the second surface of the substrate and extending in the second direction, and a via contact through the substrate, a first end of the via contact contacting the power rail, and a second end of the via contact connected to the source/drain.