Patents by Inventor Suk Pil Kim

Suk Pil Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318573
    Abstract: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate insulation layer formed on a silicon substrate, at least one nanorod embedded in the gate insulation layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate insulation layer between the source electrode and the drain electrode.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Wook Moon, Joong S. Jeon, Jung-hyun Lee, Nae-In Lee, Yeon-Sik Park, Hwa-Sung Rhee, Ho Lee, Se-Young Cho, Suk-Pil Kim
  • Patent number: 9219168
    Abstract: A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: December 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Soo Seol, Yoon-dong Park, Suk-Pil Kim
  • Patent number: 8958002
    Abstract: An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jun Choi, Yoon-Dong Park, Chris Hong, Dae-Lok Bae, Jung-Chak Ahn, Chang-Rok Moon, June-Mo Koo, Suk-Pil Kim, Hoon-Sang Oh
  • Patent number: 8937711
    Abstract: A sensor, including a plurality of photo gate pairs on a semiconductor substrate, each of the photo gate pairs including a first photo gate and a second photo gate, a first shared floating diffusion region in the semiconductor substrate, and a plurality of first transmission transistors on the semiconductor substrate, wherein each of the plurality of first transmission transistors is adapted to transmit charges to the first shared floating diffusion region in response to a first transmission control signal, the charges being generated in the semiconductor substrate under the first photo gate of each of the plurality of photo gate pairs.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: January 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk Pil Kim, Yoon Dong Park, Dong Seok Suh, Young Gu Jin, Seung Hoon Lee
  • Publication number: 20140048853
    Abstract: An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.
    Type: Application
    Filed: October 28, 2013
    Publication date: February 20, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jun Choi, Yoon-Dong Park, Chris Hong, Dae-Lok Bae, Jung-Chak Ahn, Chang-Rok Moon, June-Mo Koo, Suk-Pil Kim, Hoon-Sang Oh
  • Patent number: 8625016
    Abstract: Image sensors include a second photoelectric conversion device disposed in a lower portion of a substrate and a first photoelectric conversion device extending between the secondary photoelectric conversion device and a light receiving surface of the substrate. Electrical isolation between the first and second photoelectric conversion devices is provided by a photoelectron barrier, which may be an optically transparent electrically insulating material. MOS transistors may be utilized to transfer photoelectrons generated within the first and second photoelectric conversion devices to a floating diffusion region within the image sensor. These transistors may represent one example of means for transferring photoelectrons generated in the first and second photoelectric conversion devices to a floating diffusion region in the substrate, in response to first and second gating signals, respectively. The first and second gating signals may be active during non-overlapping time intervals.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eric Fossum, Suk Pil Kim, Yoon Dong Park, Hoon Sang Oh, Hyung Jin Bae, Tae Eung Yoon
  • Publication number: 20130344664
    Abstract: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.
    Type: Application
    Filed: August 22, 2013
    Publication date: December 26, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Wook MOON, Joong S. JEON, Jung-hyun LEE, Nae-In LEE, Yeon-Sik PARK, Hwa-Sung RHEE, Ho LEE, Se-Young CHO, Suk-Pil KIM
  • Patent number: 8570409
    Abstract: An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jun Choi, Yoon-Dong Park, Chris Hong, Dae-Lok Bae, Jung-Chak Ahn, Chang-Rok Moon, June-Mo Koo, Suk-Pil Kim, Hoon-Sang Oh
  • Patent number: 8379480
    Abstract: A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: February 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-soo Seol, Yoon-dong Park, Suk-pil Kim
  • Patent number: 8299520
    Abstract: According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Yoon-dong Park, Jae-young Choi, June-mo Koo, Byung-hee Hong
  • Patent number: 8283711
    Abstract: Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-gu Jin, Yoon-dong Park, Won-joo Kim, Seung-hoon Lee, Suk-pil Kim
  • Patent number: 8274067
    Abstract: Memory devices and methods of manufacturing the same are provided. In a memory device, a memory-switch structure is formed between a first and second electrode. The memory-switch structure includes a memory resistor and a switch structure. The switch structure controls current supplied to the memory resistor. A memory region of the memory resistor and a switch region of the switch structure are different from each other.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-eon Ahn, Myoung-jae Lee, Suk-pil Kim, Young-soo Park
  • Publication number: 20120155170
    Abstract: A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.
    Type: Application
    Filed: February 10, 2012
    Publication date: June 21, 2012
    Inventors: Kwang-soo SEOL, Yoon-dong PARK, Suk-pil KIM
  • Publication number: 20120119180
    Abstract: Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.
    Type: Application
    Filed: January 23, 2012
    Publication date: May 17, 2012
    Inventors: June-mo KOO, Suk-pil KIM, Tae-Eung YOON
  • Patent number: 8159017
    Abstract: A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-soo Seol, Yoon-dong Park, Suk-pil Kim
  • Patent number: 8124968
    Abstract: Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: June-mo Koo, Suk-pil Kim, Tae-Eung Yoon
  • Patent number: 8120006
    Abstract: Provided is a non-volatile memory device having a stacked structure that is easily highly integrated and a method of economically fabricating the non-volatile memory device. The non-volatile memory device may include at least one first electrode and at least one second electrode that cross each other. At least one data storage layer may be disposed on a section where the at least one first electrode and the at least one second electrode cross each other. The at least one first electrode may include a first conductive layer and a first semiconductor layer.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, June-mo Koo, Tae-eung Yoon
  • Patent number: 8064254
    Abstract: A non-volatile memory device includes at least one semiconductor column having a first sidewall and a second sidewall. The device also includes at least one gate electrode is disposed on the first sidewall and at least one control gate electrode disposed on the second sidewall. The device further includes at least one charge storage layer is disposed between the second sidewall and the at least one control gate electrode. The at least one gate electrode and the at least one control gate electrode may be disposed on opposite sides of the at least one semiconductor column such that they commonly control a channel region in the semiconductor column.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: November 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Yoon-dong Park
  • Patent number: 8058701
    Abstract: Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok-kee Kim, Yoon-dong Park, Seung-hoon Lee, I-hun Song, Won-joo Kim, Young-gu Jin, Hyuk-soon Choi, Suk-pil Kim
  • Patent number: 8053822
    Abstract: Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Young-gu Jin, Yoon-dong Park