Abstract: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Abstract: A semiconductor package includes at least two semiconductor chips stacked to have step surfaces and possessing bonding pads disposed over the step surfaces. Conductive patterns are disposed over the step surfaces and electrically connect the bonding pads of the semiconductor chips with one another. An insulation member is formed over side and upper surfaces of the stacked semiconductor chips excluding the step surfaces and the conductive patterns.

Abstract: A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit.

Abstract: A cube semiconductor package includes one or more stacked together and interconnected semiconductor chip modules. The cube semiconductor package includes a semiconductor chip module and connection members. The semiconductor chip module includes a semiconductor chip which has a first and second surface, side surfaces, bonding pads, through-electrodes and redistribution lines. The second surface faces away from the first surface. The side surfaces connect to the first and second surfaces. The bonding pads are placed on the first surface. The through-electrodes pass through the first and second surfaces. The redistribution lines are placed at least on one of the first and second surfaces and are electrically connected to the through-electrodes and the bonding pads, and have ends flush with the side surfaces. The connection members are placed on the side surfaces and electrically connected with the ends of the redistribution lines.

Abstract: Separate multicolorant and monochromatic digital image marking engines are operated concurrently for print jobs having both monochromatic and color images. The marked multicolorant image sheets are batch printed and held in a sheet buffer and interspersed in sequence with the monochromatic marked sheets without interrupting the faster monochromatic marking engine or requiring multiple unnecessary run cost increasing start up and shut down cycles of the multicolorant marking engine.

Abstract: Disclosed is a method for cryopreserving an oocyte by adding an antifreeze protein to a cryopreservation liquid (equilibrium solution, vitrification solution). The disclosed cryopreservation method of an oocyte minimizes damage to the oocyte, which increases the survival rate of the oocyte after freezing and thawing of the oocyte, and improves a fertilization rate, and a blastocyst development ratio of the oocyte.

Abstract: A low power frequency divider and a low power phase locked loop, which consume the least power. The low power frequency divider generates a frequency dividing signal by dividing a frequency of an input signal in a uniform ratio, and includes a phase to voltage converter, a comparator, a phase synchronization circuit, and a reset circuit. The phase to voltage converter generates a phase voltage signal corresponding to phase change of the input signal in response to a reset signal. The comparator generates a comparator signal by comparing the phase voltage signal and a reference phase voltage signal. The phase synchronization circuit generates the frequency dividing signal by matching phases of the input signal and the comparator signal. The reset circuit generates the reset signal in response to the comparator signal or the frequency dividing signal.

Abstract: This invention relates to a pharmaceutical composition containing 4-[(4-thiazolyl)phenoxyl]alkoxy-benzamidine derivatives expressed by the following formula 1 for the prophylaxis and treatment of osteoporosis and more particularly, to the use of 4-{5-[4-(5-isoproply-2-methyl-1,3-thiazol-4-yl)phenoxyl]pentoxy}-benzamidine or N-hydroxy-4-{5-[4-(5-isopropyl-2-methyl-1,3-thiazol-4-yl)phenoxyl]pentoxy}-benzamidine expressed by the following formula 1 as a pharmaceutical composition for the prophylaxis and treatment of osteoporosis.

Abstract: A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.

Abstract: A method of treating osteoporosis comprising administering to a subject a composition comprising a compound, 4-{5-[4-(5-isopropyl-2-methyl-1,3-thiazol-4-yl)phenoxy]pentoxy}-benzamidine or a salt thereof, is described. A method of inhibiting osteoclast activity and stimulating osteoblast activity in a subject also is described.

Abstract: A semiconductor package having an internal cooling system is presented which includes a semiconductor chip and a through-electrode. The semiconductor chip has a circuit section. The through-electrode passes through an upper surface and a lower surface the semiconductor chip. The through-electrode is electrically connected with the circuit section of the semiconductor chip. The through-electrode also has a through-hole for allowing cooling fluid to flow therethrough.

Abstract: A semiconductor package having a stacked wafer level structure includes a base substrate; a semiconductor chip; a redistribution pattern; and a second insulation layer pattern. The base substrate having a chip region and a peripheral region disposed at the periphery of the chip region. The semiconductor chip is disposed over the chip region and has a bonding pad. The first insulation layer pattern covers the chip region and the peripheral region and exposes the bonding pad. The redistribution pattern is disposed over the first insulation layer pattern and extends from the bonding pad to the peripheral region. The second insulation layer pattern is disposed over the first insulation layer pattern and opening some portion of the redistribution pattern disposed in the peripheral region.

Abstract: A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.

Abstract: A semiconductor package having an internal cooling system is presented which includes a semiconductor chip and a through-electrode. The semiconductor chip has a circuit section. The through-electrode passes through an upper surface and a lower surface the semiconductor chip. The through-electrode is electrically connected with the circuit section of the semiconductor chip. The through-electrode also has a through-hole for allowing cooling fluid to flow therethrough.

Abstract: A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.

Abstract: Disclosed is a sheet buffering and inverting device having a sheet transport path and multiple sheet inverter paths extending upward and/or downward there from. Sheets being transported through the sheet transport path are selectively diverted into the sheet inverter paths, held, and subsequently fed back into the sheet transport path such that they are inverted. Optionally, an additional sheet transport path can branch off the sheet transport path upstream of the sheet inverter paths and can connect to the distal end of each of the sheet inverter paths to allow sheets to be buffered without being inverted. This device can be incorporated into a discrete module of a modular printing system to ensure sheets are properly merged and oriented after processing by multiple printing engines. Alternatively, it can be incorporated into a standalone printing system to ensure sheets are properly buffered and/or inverted prior to processing by a single printing engine.

Abstract: A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.

Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

Abstract: A method of forming a photomask includes providing a layout of design patterns, setting an optical proximity correction (OPC) with respect to the layout of design patterns, and forming a layout of correction patterns with respect to the layout of design patterns by using the set OPC. The method also includes collecting verification data about the layout of correction patterns by using a layout of contour patterns based on the layout of correction patterns, and verifying whether the layout of design patterns and the layout of correction patterns are substantially identical to each other by using the verification data.

Abstract: A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.