Abstract: In the present invention, it was confirmed that the modified protein in which the 356th serine of Runx3 is substituted with alanine has an increased activity of maintaining the complex with Brd2 by more than 10 times compared to the wild-type Runx3, and the apoptosis effect is improved in various cancer cell lines compared to the wild-type Runx3. Therefore, the modified protein in which the 356th serine of Runx3 is substituted with an amino acid that cannot be phosphorylated by a kinase of the present invention, the polynucleotide coding thereof, the vector carrying the polynucleotide, or the virus or cell transformed with the vector can be used as a therapeutic agent for various cancers.

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.

Abstract: A storage device including a nonvolatile memory device that includes a nonvolatile memory cell array including a string including first and second memory cells stacked sequentially, and an OTP memory cell array that stores reference count values, the first and second memory cells respectively connected to first and second word lines; a controller including a processor that generates a read command for the first memory cell; a read level generator including a counter that receives the read command and calculates an off-cell count value of memory cells connected to the second word line, and a comparator that receives a first reference count value from the OTP memory cell array, compares the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determines a read level of the first memory cell based on the threshold voltage shift.

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A display apparatus having a mura compensation function includes a mura memory in which compensation data corresponding to coefficient values of a mura compensation equation is stored; and a mura compensation circuit configured to perform mura compensations on display data by using the mura compensation equation to which the compensation data has been applied, wherein the coefficient values are set so that the mura compensation equation has been fit to have a curve that satisfies known difference values of selected gray levels, a first estimation difference value of a first estimation gray level higher than the selected gray levels, and a second estimation difference value of a second estimation gray level lower than the selected gray levels, and wherein the compensation data comprises the coefficient values of the mura compensation equation in which all of the known difference values of the selected gray levels, the first estimation difference value, and the second estimation difference value have a differen

Abstract: A semiconductor package may include a first die disposed on a package substrate, a second die stacked on the first die, and a first position checker disposed on the package substrate. The first position checker may indicate a first position allowable range in which a first side of the first die can be located.

Abstract: A semiconductor package may include a first die disposed on a package substrate, a second die stacked on the first die, and a first position checker disposed on the package substrate. The first position checker may indicate a first position allowable range in which a first side of the first die can be located.

Abstract: A steering system for a vehicle includes a housing section, a rack section configured to penetrate the housing section, a case section mounted in the housing section, and a sensor section, mounted in the case section, configured to engage the rack section and sense an amount of movement of the rack section while being rotated.

Abstract: A steering apparatus for a vehicle includes: a rack housing; a rack bar inserted into an inner portion of the rack housing and moving linearly in a lengthwise direction of the rack housing; a housing mounted on the rack housing; a first sensing section mounted on the housing to sense an amount of movement of the rack bar while being rotated in mesh with the rack bar as the rack bar moves linearly on the rack housing; and a second sensing section mounted on the rack housing to sense the amount of movement of the rack bar within an on-center section.

Abstract: A steering system for a vehicle includes a housing section, a rack section configured to penetrate the housing section, a case section mounted in the housing section, and a sensor section, mounted in the case section, configured to engage the rack section and sense an amount of movement of the rack section while being rotated.

Abstract: A steering device for a vehicle, the steering device including: a rack housing unit; a rack drive unit inserted into the rack housing unit and configured to be movable in an axial direction; a casing unit coupled to the rack housing unit; a rotary unit mounted in the casing unit and configured to engage with the rack drive unit and be rotatable; and a detection unit mounted on the casing unit and configured to measure a rotation of the rotary unit, thereby implementing a degree of shape freedom and simplifying an assembly structure.

Abstract: A semiconductor package includes a base substrate; a printed circuit board disposed on the base substrate; a first chip stack disposed on the base substrate on one side of the printed circuit board, and including first semiconductor chips offset-stacked in a first offset direction facing the printed circuit board; a second chip stack disposed on the first chip stack, and including second semiconductor chips offset-stacked in a second offset direction facing away from the printed circuit board; a third chip stack disposed on the base substrate on the other side of the printed circuit board, and including third semiconductor chips offset-stacked in the second offset direction; and a fourth chip stack disposed on the third chip stack, and including fourth semiconductor chips offset-stacked in the first offset direction, wherein the second and fourth chip stacks are electrically connected with the base substrate through the printed circuit board.

Abstract: A semiconductor package may include a first die disposed on a package substrate, a second die stacked on the first die, and a first position checker disposed on the package substrate. The first position checker may indicate a first position allowable range in which a first side of the first die can be located.

Abstract: A semiconductor package includes a base substrate; a printed circuit board disposed on the base substrate; a first chip stack disposed on the base substrate on one side of the printed circuit board, and including first semiconductor chips offset-stacked in a first offset direction facing the printed circuit board; a second chip stack disposed on the first chip stack, and including second semiconductor chips offset-stacked in a second offset direction facing away from the printed circuit board; a third chip stack disposed on the base substrate on the other side of the printed circuit board, and including third semiconductor chips offset-stacked in the second offset direction; and a fourth chip stack disposed on the third chip stack, and including fourth semiconductor chips offset-stacked in the first offset direction, wherein the second and fourth chip stacks are electrically connected with the base substrate through the printed circuit board.

Abstract: A semiconductor package includes: a substrate; a first interposer disposed over the substrate; a first chip stack disposed on the substrate on one side of the first interposer, wherein the first chip stack includes a plurality of first semiconductor chips stacked with an offset in a first direction; a second chip stack disposed on the first chip stack, wherein the second chip stack includes a plurality of second semiconductor chips stacked with an offset in a second direction opposite to the first direction; and a third chip stack disposed on the substrate on an other side of the first interposer, wherein the third chip stack includes a plurality of third semiconductor chips stacked with an offset in the second direction.

Abstract: A semiconductor package includes: a substrate; a first interposer disposed over the substrate; a first chip stack disposed on the substrate on one side of the first interposer, wherein the first chip stack includes a plurality of first semiconductor chips stacked with an offset in a first direction; a second chip stack disposed on the first chip stack, wherein the second chip stack includes a plurality of second semiconductor chips stacked with an offset in a second direction opposite to the first direction; and a third chip stack disposed on the substrate on an other side of the first interposer, wherein the third chip stack includes a plurality of third semiconductor chips stacked with an offset in the second direction.

Abstract: An indexing apparatus and method for search of security monitoring data are provided. The indexing apparatus includes a data collection unit and a data index generation unit. The data collection unit collects data, that is, a basis of search of monitoring information, from a database in which security monitoring data has been stored. The data index generation unit generates file structure-based data in which indices have assigned to multiple search elements of the data collected by the data collection unit.

Abstract: A pickup apparatus includes a plurality of pickers sliding along a first direction and a space adjuster including a plurality of space adjusting plates. Each picker includes a protruding portion combined with a picker body, and each of the space adjusting plates is between a respective pair of adjacent pickers. The protruding portion of each picker contacts sidewalls of adjacent space adjusting plates. At least one of the space adjusting plates moves along a second direction crossing the first direction. A width in the first direction of each space adjusting plate varies along the second direction.

Abstract: A pickup apparatus includes a plurality of pickers sliding along a first direction and a space adjuster including a plurality of space adjusting plates. Each picker includes a protruding portion combined with a picker body, and each of the space adjusting plates is between a respective pair of adjacent pickers. The protruding portion of each picker contacts sidewalls of adjacent space adjusting plates. At least one of the space adjusting plates moves along a second direction crossing the first direction. A width in the first direction of each space adjusting plate varies along the second direction.

Abstract: A semiconductor device including a substrate including a first and second region; a first active region formed in an upper portion of the substrate in the first region; a second active region formed in an upper portion of the substrate in the second region; a first gate structure extending across the first active region, having a first gate length, and including a first high-k dielectric layer, a first lower metal layer, and a first upper metal layer; a second gate structure extending across the second active region, having a second gate length, and including a second high-k dielectric layer, a second lower metal layer having at least one metal layer, and a second upper metal layer; and spacers at sides of each of the first and second gate structures, a cross section of each of the first and second high-k dielectric layers has a U-shape, a cross section of each of the first and second lower metal layers has a U-shape, the first and second lower metal layers covering bottom surfaces and inner side surfaces of