Patents by Inventor Sumanesh Samanta

Sumanesh Samanta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10423357
    Abstract: A method for managing a pool buffers includes establishing a first buffer class with a first allowable number of buffers, and a first reserved number of buffers that are reserved for the first buffer class in the pool of buffers even if no Input/Output (I/O) operation is running in connection with the first buffer class. The method includes establishing a second buffer class with a second allowable number of buffers, and a second reserved number of buffers that are reserved for the second buffer class in the pool of buffers even if no I/O operation is running in connection with the second buffer class. The first buffer is enabled class to have more than the first allowable number of buffers as long as a number of buffers allocated to the second buffer class is fewer than the second allowable number of buffers.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: September 24, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Horia Simionescu, Allen Kelton, Timothy Hoglund, Sumanesh Samanta
  • Publication number: 20180335974
    Abstract: A method for managing a pool buffers includes establishing a first buffer class with a first maximum allowable number of buffers, and a first reserved number of buffers that are reserved for the first buffer class in the pool of buffers even if no Input/Output (I/O) operation is running in connection with the first buffer class. The method includes establishing a second buffer class with a second maximum allowable number of buffers, and a second reserved number of buffers that are reserved for the second buffer class in the pool of buffers even if no I/O operation is running in connection with the second buffer class. The first buffer is enabled class to have more than the first maximum allowable number of buffers as long as a number of buffers allocated to the second buffer class is fewer than the second maximum allowable number of buffers.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Inventors: Horia Simionescu, Allen Kelton, Timothy Hoglund, Sumanesh Samanta
  • Patent number: 9921753
    Abstract: Embodiments herein provide for redundant data storage. One storage system includes first and second host systems each comprising a memory and a persistent storage device. The storage system also includes first and second storage controllers each comprising a memory (e.g., DRAM). The memory of the first storage controller is mapped to the memory of the first host system and the memory of the second storage controller is mapped to the memory of the second host system. The first storage controller is operable to DMA data from the persistent storage device of the first host system to the memory of the first storage controller, and to direct the second storage controller to DMA the data to the persistent storage device of the second host system via the memory of the second storage controller.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: March 20, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Sumanesh Samanta, Luca Bert, Naveen Krishnamurthy
  • Patent number: 9886386
    Abstract: An apparatus having a cache and a controller is disclosed. The controller is configured to (i) gather a plurality of statistics corresponding to a plurality of requests made from one or more hosts to access a memory during an interval, (ii) store data of the requests selectively in the cache in response to a plurality of headers and (iii) adjust one or more parameters in the headers in response to the statistics. The requests and the parameters are recorded in the headers.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 6, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Mark Ish, Sumanesh Samanta
  • Patent number: 9542327
    Abstract: Methods and structure for selective cache mirroring. One embodiment includes a control unit and a memory. The memory is able to store indexing information for a multi-device cache for a logical volume. The control unit is able to receive an Input/Output (I/O) request from a host directed to a Logical Block Address (LBA) of the logical volume, to consult the indexing information to identify a cache line for storing the I/O request, and to store the I/O request at the cache line on a first device of the cache. The control unit is further able to mirror the I/O request to another device of the cache if the I/O request is a write request, and to complete the I/O request without mirroring the I/O request to another device of the cache if the I/O request is a read request.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: January 10, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sumanesh Samanta, Saugata Das Purkayastha, Sourav Saha, Mohana Rao Goli
  • Patent number: 9542320
    Abstract: Systems and methods maintain cache coherency between storage controllers using input/output virtualization. In one embodiment, a primary storage controller receives write commands over a virtualized interface, stores the write commands in cache memory, tracks a status of the write commands processed from the cache memory, and stores the status in a portion of the cache memory. A backup storage controller includes a backup cache that receives replications of the write commands via direct memory access operations, and stores the replications of the write commands. The primary storage controller makes the status available to a host system. In response to a failure of the primary storage controller, the backup storage synchronizes with the status from the host system, and resumes I/O operations for the logical volume.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: January 10, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Luca Bert, Sumanesh Samanta, Philip K. Wong
  • Patent number: 9524201
    Abstract: Systems and methods to safely and efficiently handle dirty data flush are disclosed. More specifically, when a cache controller determines that one (or more) storage device of a cache device is running out of space, that storage device is given priority to be flushed prior to the other storage devices that are not in such a critical condition. In addition, a cache bypass process can be conditionally enabled to save free physical spaces already running low on such critical cache storage devices.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 20, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sumanesh Samanta, Srikanth Krishnamurthy Sethuramachar, Ramkumar Venkatachalam
  • Publication number: 20160283379
    Abstract: Methods and structure for utilizing linked lists to flush a cache. One exemplary embodiment includes a memory, an interface, and an Input/Output (I/O) processor. The memory implements a cache divided into cache lines, and the interface receives I/O directed to a block address of a storage device. The I/O processor determines a remainder by dividing the block address by the number of cache lines, and selects a cache line for storing the I/O based on the remainder. The I/O processor determines a quotient by dividing the block address by the number of cache lines, and associates the quotient with the selected cache line. Additionally, the I/O processor populates a linked list by inserting entries that each point to a different cache line associated with the same quotient, and flushes the cache lines to the storage device in block address order by traversing the entries of the linked list.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Sumanesh Samanta, Horia Cristian Simionescu, Ashish Jain
  • Publication number: 20160283134
    Abstract: Embodiments herein provide for redundant data storage. One storage system includes first and second host systems each comprising a memory and a persistent storage device. The storage system also includes first and second storage controllers each comprising a memory (e.g., DRAM). The memory of the first storage controller is mapped to the memory of the first host system and the memory of the second storage controller is mapped to the memory of the second host system. The first storage controller is operable to DMA data from the persistent storage device of the first host system to the memory of the first storage controller, and to direct the second storage controller to DMA the data to the persistent storage device of the second host system via the memory of the second storage controller.
    Type: Application
    Filed: March 23, 2015
    Publication date: September 29, 2016
    Inventors: Sumanesh Samanta, Luca Bert, Naveen Krishnamurthy
  • Publication number: 20160203080
    Abstract: Systems and methods maintain cache coherency between storage controllers using input/output virtualization. In one embodiment, a primary storage controller receives write commands over a virtualized interface, stores the write commands in cache memory, tracks a status of the write commands processed from the cache memory, and stores the status in a portion of the cache memory. A backup storage controller includes a backup cache that receives replications of the write commands via direct memory access operations, and stores the replications of the write commands. The primary storage controller makes the status available to a host system. In response to a failure of the primary storage controller, the backup storage synchronizes with the status from the host system, and resumes I/O operations for the logical volume.
    Type: Application
    Filed: January 12, 2015
    Publication date: July 14, 2016
    Inventors: Luca Bert, Sumanesh Samanta, Philip Wong
  • Patent number: 9378152
    Abstract: A storage subsystem can achieve more efficient I/O processing by enabling users to specify and pass out of band I/O hints comprising an object to be hinted, a hint type, and caching strategies associated with a hint type. A hinted object may be either a virtual device or a file. In addition to priority cache, hint types may include never-cache, sticky-cache, and volatile-cache. Hints may be passed via command-line or graphical-user interfaces.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: June 28, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Kishore Kaniyar Sampathkumar, Parag Maharana, Sumanesh Samanta, Saugata Das Purkayastha
  • Patent number: 9317211
    Abstract: A system and method for managing the life expectancy of at least one solid state drive (SSD) within a cache device of a storage subsystem includes determining a baseline rate of decline for each SSD based on its guaranteed life expectancy. At intervals, each SSD of the cache device is polled for remaining life and power-on time, and a current rate of decline (based on time since initialization) and a cumulative rate of decline (based on total lifespan of the SSD) is determined. When both the current rate of decline and the cumulative rate of decline exceed the baseline rate of decline for any SSD of the cache device, write requests to that SSD are blocked and redirected to the virtual device until either the current rate of decline or cumulative rate of decline drop below the baseline rate.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: April 19, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sumanesh Samanta, Mohana Rao Goli, Karimulla Sheik
  • Patent number: 9292204
    Abstract: A system and method for managing cache memory of at least one node of a multiple-node storage cluster. A first cache data and a first cache metadata are stored for data transfers between a respective node and regions of a storage cluster receiving at least a first selected number of data transfer requests. When the node is rebooted, a second (new) cache data is stored to replace the first (old) cache data. The second cache data is compiled utilizing the first cache metadata to identify previously cached regions of the storage cluster receiving at least a second selected number of data transfer requests after the node is rebooted. The second selected number of data transfer requests is less than the first selected number of data transfer requests to enable a rapid build of the second cache data.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 22, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sumanesh Samanta, Sujan Biswas, Horia Cristian Simionescu, Luca Bert, Mark Ish
  • Patent number: 9286175
    Abstract: The disclosure is directed to preserving data consistency in a multiple-node data storage system. According to various embodiments, a write log is maintained including log entries for data transfer requests being served by a respective node of the multiple-node data storage system. Rather than maintaining a full write journal of data and parity associated with each data transfer request, the log entries only need to identify portions of the virtual volume being updated according to the data transfer requests served by each node. When a first node fails, a second node takes over administration of a virtual volume for the failed node. Upon taking over for the first (failed) node, the second node resolves any inconsistencies between data and parity in portions of the virtual volume identified the respective log entries. Accordingly, write holes are prevented without substantially increasing memory usage or system complexity.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 15, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sumanesh Samanta, Horia Cristian Simionescu, Luca Bert, Debal Kr. Mridha, Mohana Rao Goli
  • Patent number: 9262346
    Abstract: A method generates input/output (IO) commands by plural different applications that execute on a host. The method prioritizes the applications by inserting different classifiers into the IO commands at a host bus adapter (HBA) located in the host. A storage device receives the IO commands and processes the IO commands according to priorities based on the classifiers for the applications.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: February 16, 2016
    Assignee: Hewlett Packard Enterprises Development LP
    Inventors: Kishore Kumar Muppirala, Satish Kumar Mopur, Dinkar Sitaram, Sumanesh Samanta, Ayman Abouelwafa
  • Publication number: 20160026575
    Abstract: Methods and structure for selective cache mirroring. One embodiment includes a control unit and a memory. The memory is able to store indexing information for a multi-device cache for a logical volume. The control unit is able to receive an Input/Output (I/O) request from a host directed to a Logical Block Address (LBA) of the logical volume, to consult the indexing information to identify a cache line for storing the I/O request, and to store the I/O request at the cache line on a first device of the cache. The control unit is further able to mirror the I/O request to another device of the cache if the I/O request is a write request, and to complete the I/O request without mirroring the I/O request to another device of the cache if the I/O request is a read request.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 28, 2016
    Inventors: Sumanesh Samanta, Saugata Das Purkayastha, Sourav Saha, Mohana Rao Goli
  • Publication number: 20160026579
    Abstract: A cache controller having a cache supported by a non-volatile memory element manages metadata operations by defining a mathematical relationship between a cache line in a data store exposed to a host system and a location identifier associated with an instance of the cache line in the non-volatile memory. The cache controller maintains most recently used bit maps identifying data in the cache, as well as a data characteristic bit map identifying data that has changed since it was added to the cache. The cache controller maintains a most recently used bit map to replace the recently map at an appropriate time and a fresh bitmap tracks the most recently used bit map. The cache controller uses a collision bitmap, an imposter index and a quotient to modify cache lines stored in the non-volatile memory element.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 28, 2016
    Inventors: Sumanesh Samanta, Suagata Das Purkayastha, Mark Ish, Horia Simionescu, Luca Bert
  • Patent number: 9244868
    Abstract: A method and system for IO processing in a storage system is disclosed. In accordance with the present disclosure, a controller may take long term “lease” of a portion (e.g., an LBA range) of a virtual disk of a RAID system and then utilize local locks for IOs directed to the leased portion. The method and system in accordance with the present disclosure eliminates inter-controller communication for the majority of IOs and improves the overall performance for a High Availability Active-Active DAS RAID system.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: January 26, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sumanesh Samanta, Sujan Biswas, Horia Simionescu
  • Publication number: 20160004644
    Abstract: A storage controller maintaining a cache manages modified data flush operations. A set-associative map or relationship between individual cache lines in the cache and a corresponding portion of the host managed or source data store is generated in such a way that a quotient can be used to identify modified data in the cache in the order of the source data's logical block addresses. The storage controller uses a collision bitmap, a dirty bit map and a flush table when flushing data from the cache. The storage controller selects a quotient and identifies modified cache lines in the cache identified by the quotient. As long as the quotient remains the same, the storage controller flushes or transfers the modified cache lines to the data store. Otherwise, when the quotient is not the same, the data in the cache is skipped. A linked list is used to traverse skipped cache lines.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Inventors: Sumanesh Samanta, Mark Ish, Suagata Das Purkayastha
  • Publication number: 20150370715
    Abstract: Systems and methods to safely and efficiently handle dirty data flush are disclosed. More specifically, when a cache controller determines that one (or more) storage device of a cache device is running out of space, that storage device is given priority to be flushed prior to the other storage devices that are not in such a critical condition. In addition, a cache bypass process can be conditionally enabled to save free physical spaces already running low on such critical cache storage devices.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 24, 2015
    Inventors: Sumanesh Samanta, Srikanth Krishnamurthy Sethuramachar, Ramkumar Venkatachalam