Abstract: Systems and methods for performing operations on memory of a computing device are disclosed. According to an aspect, a method includes storing update data on a first memory of a computing device, wherein the update data comprises data for updating a second memory on the computing device. The method also includes initiating an update mode on the second memory. Further, the method includes suspending an I/O operation of the second memory. The method also includes switching the computing device to a system management mode (SMM) while the second memory is in the update mode. Further, the method includes retrieving the update data from the first memory. The method also includes determining whether the update data is valid. The method also includes resuming the I/O operation of the second memory for updating the second memory based on the retrieved update data in response to determining that the update data is valid.

Abstract: A method includes running servers to provide computer services to client devices and storing a hardware profile for each of a plurality of server models, wherein each hardware profile identifies hardware components that should be enabled to implement the server model on one of the servers. A request is received from a client device to provide computer services on one or more of the servers using a selected server model and applying the hardware profile for the selected server model to configure the hardware components of the one or more of the servers to use the identified hardware components without manually reconfiguring the one or more of the servers. Still further, the method includes providing computer services to the client device using the one or more of the servers that has been configured using the hardware profile for the selected server model.

Abstract: A method includes running a scale-up hypervisor on a server complex including at least one server and running a single operating system and at least one application on top of the scale-up hypervisor. The method further includes identifying a firmware update available for a first hardware component within the server complex. The scale-up hypervisor removes all workload from the first hardware component, and the identified firmware update is applied to the first hardware component while the first hardware component is idle and the hypervisor continues running the single operating system and the at least one application. Preferably, the method may be used to sequentially apply firmware updates to various hardware components across the plurality of servers without ever shutting down the entire plurality of servers.

Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.

Abstract: In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

Abstract: In a method of memory testing in a data processing system, in response to receiving a request for a hardware memory test during boot process of the data processing system, a controller accesses a stored past memory test result. The past memory test result includes at least a first number of test loops used in a past memory test, an identification of a first test pattern, and an error that occurred in the past memory test. The controller adjusts a second number of test loops and a second test pattern to be used in the hardware memory test according to the past memory test result. The controller then performs the hardware memory test according to the adjusted second number of test loops and the second test pattern.

Abstract: In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

Abstract: Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests.

Abstract: Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests.

Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Abstract: Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.

Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.

Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.

Abstract: In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

Abstract: In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.

Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.

Abstract: Embodiments comprise systems, methods and media for updating CRTM code in a computing machine. In one embodiment, the CRTM code initially resides in ROM and updated CRTM is stored in a staging area of the ROM. A logical partition of L2 cache may be created to store a heap and a stack and a data store. The data store holds updated CRTM code copied to the L2 cache. When a computing system is started, it first executes CRTM code. The CRTM code checks the staging area of the ROM to determine if there is updated CRTM code. If so, then CRTM code is copied into the L2 cache to be executed from there. The CRTM code loads the updated code into the cache and verifies its signature. The CRTM code then copies the updated code into the cache where the current CRTM code is located.

Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.