Patents by Inventor Sun-Hak Lee
Sun-Hak Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966919Abstract: Various example embodiments of the disclosure relate to an electronic device and a wireless communication connection control method thereof.Type: GrantFiled: March 14, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Ho Kang, Jinhyun Park, Ye-Ji Yoon, Jun-Hak Lim, Wontae Chae, Jongmu Choi, Bokun Choi, Doo-Suk Kang, Sun-Kee Lee, Moonsoo Kim, Eun Jung Hyun
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Publication number: 20220263268Abstract: The present disclosure relates to a receptacle connector, comprising a plurality of contacts for electrically connecting a plug connector and a substrate which is provided in an electronic device; an insulating part; a shell; and a sealing part for sealing between the electronic device and the shell, wherein the shell includes a shell body, and a first support part, wherein the first support part may include a first rear support member; a first outer support member which protrudes forward from the first rear support member; a first connecting member which is coupled to the front of the first outer support member; and a first inner support member which is coupled to each of the first connecting member and the shell body and is disposed spaced apart from the first outer support member.Type: ApplicationFiled: April 9, 2021Publication date: August 18, 2022Inventors: Hyun Woo LEE, Jung Hoon CHOI, Sun Hak LEE
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Patent number: 11183495Abstract: A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate.Type: GrantFiled: July 25, 2019Date of Patent: November 23, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sun-hak Lee, Yong Zhong Hu, Hye-mi Kim
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Publication number: 20190348412Abstract: A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate.Type: ApplicationFiled: July 25, 2019Publication date: November 14, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sun-hak LEE, Yong Zhong HU, Hye-mi KIM
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Patent number: 10366981Abstract: A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate. The diode part includes a p-type body region disposed inside the substrate and electrically connected with the anode terminal, an n-type well disposed on one side of the p-type body region and having a first impurity concentration, and a first n-type semiconductor region disposed below the p-type body region and having a second impurity concentration which is lower than the first impurity concentration.Type: GrantFiled: September 4, 2015Date of Patent: July 30, 2019Assignee: Semiconductor Components Industries, LLCInventors: Sun-hak Lee, Yong Zhong Hu, Hye-mi Kim
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Patent number: 10312322Abstract: A power semiconductor device includes a substrate including a first epitaxial layer, a second epitaxial layer, and a base substrate where the first epitaxial layer is disposed between the second epitaxial layer and the base substrate. The power semiconductor device includes an anode electrode and a cathode electrode disposed on the substrate, a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity. The power semiconductor device includes an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration. The power semiconductor device includes an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.Type: GrantFiled: April 13, 2018Date of Patent: June 4, 2019Assignee: Semiconductor Components Industries, LLCInventors: Hye-mi Kim, Sun-hak Lee
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Publication number: 20180233555Abstract: A power semiconductor device includes a substrate including a first epitaxial layer, a second epitaxial layer, and a base substrate where the first epitaxial layer is disposed between the second epitaxial layer and the base substrate. The power semiconductor device includes an anode electrode and a cathode electrode disposed on the substrate, a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity. The power semiconductor device includes an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration. The power semiconductor device includes an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hye-mi Kim, Sun-hak Lee
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Patent number: 9947742Abstract: A power semiconductor device includes: a substrate; an anode electrode and a cathode electrode disposed on the substrate; a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity; an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration; and an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.Type: GrantFiled: October 28, 2016Date of Patent: April 17, 2018Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Hye-mi Kim, Sun-hak Lee
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Publication number: 20170148873Abstract: A power semiconductor device includes: a substrate; an anode electrode and a cathode electrode disposed on the substrate; a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity; an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration; and an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.Type: ApplicationFiled: October 28, 2016Publication date: May 25, 2017Inventors: Hye-mi Kim, Sun-hak Lee
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Publication number: 20160071837Abstract: A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate. The diode part includes a p-type body region disposed inside the substrate and electrically connected with the anode terminal, an n-type well disposed on one side of the p-type body region and having a first impurity concentration, and a first n-type semiconductor region disposed below the p-type body region and having a second impurity concentration which is lower than the first impurity concentration.Type: ApplicationFiled: September 4, 2015Publication date: March 10, 2016Inventors: Sun-hak LEE, Yong Zhong HU, Hye-mi KIM
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Patent number: 9257502Abstract: In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.Type: GrantFiled: June 26, 2013Date of Patent: February 9, 2016Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Min-suk Kim, Sun-hak Lee, Jin-woo Moon, Hye-mi Kim
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Patent number: 9018186Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: GrantFiled: September 24, 2013Date of Patent: April 28, 2015Assignee: Postech Academy-Industry FoundationInventors: Jung Hwan Lee, Soon Hag Kim, Mi-Jin Kwon, Hyungu Kang, Sung Ho Ryu, Jong In Kim, Youndong Kim, Young Chan Chae, Sung Key Jang, Jong Hun Im, Sun Hak Lee, Hye Jung Lee, Eun Jung Jang, Ki Seok Kim
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Patent number: 9018185Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: GrantFiled: September 24, 2013Date of Patent: April 28, 2015Assignee: Postech Academy-Industry FoundationInventors: Jung Hwan Lee, Soon Hag Kim, Mi-Jin Kwon, Hyungu Kang, Sung Ho Ryu, Jong In Kim, Youndong Kim, Young Chan Chae, Sung Key Jang, Jong Hun Im, Sun Hak Lee, Hye Jung Lee, Eun Jung Jang, Ki Seok Kim
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Publication number: 20140213636Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: ApplicationFiled: September 24, 2013Publication date: July 31, 2014Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: JUNG HWAN LEE, SOON HAG KIM, MI-JIN KWON, HYUNGU KANG, SUNG HO RYU, JONG IN KIM, YOUNDONG KIM, YOUNG CHAN CHAE, SUNG KEY JANG, JONG HUN IM, SUN HAK LEE, HYE JUNG LEE, EUN JUNG JANG, KI SEOK KIM
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Publication number: 20140093886Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: ApplicationFiled: September 24, 2013Publication date: April 3, 2014Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: JUNG HWAN LEE, SOON HAG KIM, MI-JIN KWON, HYUNGU KANG, SUNG HO RYU, JONG IN KIM, YOUNDONG KIM, YOUNG CHAN CHAE, SUNG KEY JANG, JONG HUN IM, SUN HAK LEE, HYE JUNG LEE, EUN JUNG JANG, KI SEOK KIM
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Publication number: 20130341718Abstract: In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.Type: ApplicationFiled: June 26, 2013Publication date: December 26, 2013Inventors: Min-suk KIM, Sun-hak LEE, Jin-woo MOON, Hye-mi KIM
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Patent number: 8569252Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: GrantFiled: April 14, 2010Date of Patent: October 29, 2013Assignees: Postech Academy-Industry Foundation, PoscoInventors: Jung-Hwan Lee, Soon-Hag Kim, Mi-Jin Kwon, Hyun-Gu Kang, Sung-Ho Ryu, Jong-In Kim, Youn-Dong Kim, Young-Chan Chae, Sung-Key Jang, Jong-Hun Im, Sun-Hak Lee, Hye-Jung Lee, Eun-Jung Jang, Ki-Seok Kim
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Patent number: 8476700Abstract: A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.Type: GrantFiled: February 12, 2010Date of Patent: July 2, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Mok Kim, Sun-Hak Lee, Tae-Cheol Lee, Yong-Sang Jeong
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Patent number: 8124756Abstract: A method for preparing amino linker oligonucleotides is provided. More specifically, a method of preparing 5?-amino-linker oligonucleotides comprising the steps of: introducing an amino linker having a protecting group into the 5? terminus of an oligonucleotide; and removing the protecting group from the amino linker oligonucleotide by contacting with acetic acid and 2,2,2-trifluoroethanol is provided. The amino protecting group is efficiently removed from the amino linker oligonucleotides, and thereby achieving a high yield of the amino linker oligonucleotides.Type: GrantFiled: September 15, 2009Date of Patent: February 28, 2012Assignees: Postech Academy-Industry Foundation, PoscoInventors: Jung-Hwan Lee, Hyun-Gu Kang, Sung-Ho Ryu, Jong-In Kim, Sun-Hak Lee, Hye-Jung Lee, Eun-Jung Jang
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Publication number: 20100317723Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: ApplicationFiled: April 14, 2010Publication date: December 16, 2010Applicants: POSTECH ACADEMY-INDUSTRY FOUDATION, POSCOInventors: JUNG-HWAN LEE, SOON-HAG KIM, MI-JIN KWON, HYUN-GU KANG, SUNG-HO RYU, JONG-IN KIM, YOUN-DONG KIM, YOUNG-CHAN CHAE, SUNG-KEY JANG, JONG-HUN IM, SUN-HAK LEE, HYE-JUNG LEE, EUN-JUNG JANG, KI-SEOK KIM