Patents by Inventor Sun-Hak Lee
Sun-Hak Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100317723Abstract: Improved G-rich oligonucleotide (GRO) aptamers specific to nucleolin, a method of preparing the aptamers, and a use of the aptamers for diagnosing and/or treating a nucleolin-associated disease, are provided.Type: ApplicationFiled: April 14, 2010Publication date: December 16, 2010Applicants: POSTECH ACADEMY-INDUSTRY FOUDATION, POSCOInventors: JUNG-HWAN LEE, SOON-HAG KIM, MI-JIN KWON, HYUN-GU KANG, SUNG-HO RYU, JONG-IN KIM, YOUN-DONG KIM, YOUNG-CHAN CHAE, SUNG-KEY JANG, JONG-HUN IM, SUN-HAK LEE, HYE-JUNG LEE, EUN-JUNG JANG, KI-SEOK KIM
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Publication number: 20100207204Abstract: A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.Type: ApplicationFiled: February 12, 2010Publication date: August 19, 2010Inventors: Young-Mok Kim, Sun-Hak Lee, Tae-Cheol Lee, Yong-Sang Jeong
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Publication number: 20100093994Abstract: A method for preparing amino linker oligonucleotides is provided, wherein an amino protecting group is efficiently removed from the amino linker oligonucleotides protected by the protecting group, and thereby achieving a high yield of the amino linker oligonucleotides.Type: ApplicationFiled: September 15, 2009Publication date: April 15, 2010Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, POSCOInventors: Jung-Hwan LEE, Hyun-Gu Kang, Sung-Ho Ryu, Jong-In Kim, Sun-Hak Lee, Hye-Jung Lee, Eun-Jung Jang
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Patent number: 7618854Abstract: In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.Type: GrantFiled: February 15, 2008Date of Patent: November 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Sun-Hak Lee
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Publication number: 20090009434Abstract: An address driver includes an energy recovery circuit and an output stage connected to the energy recovery circuit. The output stage is connected to the energy recovery circuit and is formed of a pull-up MOS transistor and a pull-down MOS transistor in series. A source terminal of the pull-up MOS transistor is connected to the energy recovery circuit, and a bulk terminal of the pull-up MOS transistor is connected to a node providing a reverse bias between the source terminal and the bulk terminal of the pull-up MOS transistor. A display device employing the address driver is also provided.Type: ApplicationFiled: June 26, 2008Publication date: January 8, 2009Inventors: Yong-Don Kim, Joung-Ho Kim, Mueng-Ryul Lee, Yong-Chan Kim, Sun-Hak Lee
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Patent number: 7446000Abstract: A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.Type: GrantFiled: July 18, 2007Date of Patent: November 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-hak Lee, Kwang-dong Yoo, Sang-bae Yi, Soo-cheol Lee, Mueng-ryul Lee
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Publication number: 20080138946Abstract: In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.Type: ApplicationFiled: February 15, 2008Publication date: June 12, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sun-Hak Lee
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Patent number: 7381621Abstract: A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region.Type: GrantFiled: January 5, 2007Date of Patent: June 3, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-hak Lee, Kwang-dong Yoo
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Publication number: 20080124873Abstract: A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.Type: ApplicationFiled: July 18, 2007Publication date: May 29, 2008Inventors: Sun-hak Lee, Kwang-dong Yoo, Sang-bae Yi, Soo-cheol Lee, Mueng-ryul Lee
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Publication number: 20070105298Abstract: A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region.Type: ApplicationFiled: January 5, 2007Publication date: May 10, 2007Inventors: Sun-hak Lee, Kwang-dong Yoo
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Patent number: 7176538Abstract: A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region.Type: GrantFiled: June 3, 2004Date of Patent: February 13, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-hak Lee, Kwang-dong Yoo
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Publication number: 20060011981Abstract: In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.Type: ApplicationFiled: July 14, 2005Publication date: January 19, 2006Inventor: Sun-Hak Lee
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Patent number: 6867476Abstract: In a DMOS device, a drift region is located over a substrate and is lightly doped with impurities of a first conductivity type. A plurality of body areas are located in the drift region and doped with impurities of a second conductivity type which is opposite the first conductivity type. A plurality of source areas are respectively located in the body areas and heavily doped with impurities of the first conductivity type. A plurality of bulk areas are respectively located adjacent the source areas and in the body areas, and are heavily doped with impurities of the second conductivity type. A well region partially surrounds the body areas collectively and is doped with impurities of the first conductivity.Type: GrantFiled: March 26, 2003Date of Patent: March 15, 2005Assignee: Samsung Electronics Co., LTDInventor: Sun-Hak Lee
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Patent number: 6853040Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region. P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.Type: GrantFiled: November 20, 2002Date of Patent: February 8, 2005Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Kyung-Oun Jang, Sun-Hak Lee
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Publication number: 20040256646Abstract: A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region.Type: ApplicationFiled: June 3, 2004Publication date: December 23, 2004Inventors: Sun-hak Lee, Kwang-dong Yoo
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Publication number: 20030219945Abstract: In a DMOS device, a drift region is located over a substrate and is lightly doped with impurities of a first conductivity type. A plurality of body areas are located in the drift region and doped with impurities of a second conductivity type which is opposite the first conductivity type. A plurality of source areas are respectively located in the body areas and heavily doped with impurities of the first conductivity type. A plurality of bulk areas are respectively located adjacent the source areas and in the body areas, and are heavily doped with impurities of the second conductivity type. A well region partially surrounds the body areas collectively and is doped with impurities of the first conductivity.Type: ApplicationFiled: March 26, 2003Publication date: November 27, 2003Inventor: Sun-Hak Lee
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Publication number: 20030071314Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region . P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.Type: ApplicationFiled: November 20, 2002Publication date: April 17, 2003Applicant: Fairchild Korea Semiconductor Ltd.Inventors: Kyung-Oun Jang, Sun-Hak Lee
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Patent number: 6507080Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.Type: GrantFiled: January 17, 2001Date of Patent: January 14, 2003Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Kyung-Oun Jang, Sun-Hak Lee
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Publication number: 20010008294Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.Type: ApplicationFiled: January 17, 2001Publication date: July 19, 2001Inventors: Kyung-Oun Jang, Sun-Hak Lee
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Patent number: 6194760Abstract: There are provided a double-diffused MOS (Metal Oxide Semiconductor) transistor and a fabricating method thereof. In the double-diffused MOS transistor, a buried layer of a first conductive type and an epitaxial layer of the first conductive type are sequentially formed on a semiconductor substrate, and a gate electrode is formed on the epitaxial layer of the first conductive type with interposition of a gate insulating film. Source and drain regions of the first conductive type are formed in the surface of the epitaxial layer of the first conductive type in self-alignment and non-self-alignment with the gate electrode, respectively. A body region of a second conductive type is formed in the surface of the epitaxial layer of the first conductive type to be surrounded by the source region of the first conductive type, and a bulk bias region of the second conductive type is formed in the body region of the second conductive type under the source region of the first conductive type.Type: GrantFiled: December 18, 1998Date of Patent: February 27, 2001Assignee: Samsung Electronics Co., Ltd.Inventor: Sun-Hak Lee