Abstract: The present invention relates to a pharmaceutical composition for preventing or treating cancer containing pleiotropic regulator 1 (PLRG1) inhibitor as an active ingredient, a method for treating cancer including administering the composition to a subject, a composition for diagnosing cancer containing an agent for measuring the expression level of PLRG1, a method for providing information for diagnosing cancer including measuring the expression level of PLRG1, and a method for screening agents for preventing or treating cancer. Pleiotropic regulator 1 (PLRG1) is overexpressed in cancer cells, and the inhibition of the expression of PLRG1 can induce cancer cell-specific apoptosis. Accordingly, the PLRG1 inhibitor of the present invention has an excellent effect as an anticancer agent without side effects, and additionally, the PLRG1 inhibitor can be used for cancer diagnosis, screening of anticancer agents, etc. by measuring the expression levels of PLRG1.

Abstract: A composition for detecting a marker for the diagnosis or prognosis of liver cancer is disclosed. The composition includes an agent capable of assessing the expression level of UQCRH (ubiquinol-cytochrome c reductase hinge protein). In addition, a kit having the composition, a microarray for the diagnosis of liver cancer using the marker, and a method for detecting the marker, and predicting recurrence following surgery in liver cancer patients are disclosed. The marker is able to contribute to the early diagnosis of liver cancer and prediction of recurrence following surgery and survival of liver cancer patients who have undergone hepatic resection, and also is significant for being a promising therapeutic target for liver cancer.

Abstract: An electrochromic transparent plate which can enhance a response speed and a method for manufacturing the same are disclosed. The electrochromic transparent plate includes a pair of transparent plates spaced apart a predetermined distance from each other; a pair of transparent electrodes provided in the pair of the transparent plates, respectively; a cathodic coloration layer provided on one of the pair of the transparent electrodes, to represent a color in a cathodic state; an anodic coloration layer provided on the other one of the pair of the transparent electrodes, in opposite to the cathodic coloration layer, to represent a color in an anodic state; and an electrolyte layer provided between the cathodic coloration layer and the anodic coloration layer, to move an electron between the cathodic coloration layer and the anodic coloration layer there through as intermediate.

Abstract: A method of forming a contact structure includes forming an isolation region defining active regions in a semiconductor substrate. Gate patterns extending to the isolation region while crossing the active regions are formed. A sacrificial layer is formed on the semiconductor substrate having the gate patterns. Sacrificial patterns remaining on the active regions are formed by patterning the sacrificial layer. Molding patterns are formed on the isolation region. Contact holes exposing the active regions at both sides of the gate patterns are formed by etching the sacrificial patterns using the molding patterns and the gate patterns as an etching mask. Contact patterns respectively filling the contact holes are formed. The disclosed method of forming a contact structure may be used in fabricating a semiconductor device.

Abstract: A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.

Abstract: A washing machine equipped with a radiation drying unit includes a rotary drum for accommodating laundry therein, a water tub for accommodating the rotary drum rotatably, a far infrared radiation generator for generating a radiant ray in a far infrared wavelength range, a radiation transmission portion for transmitting the radiant ray generated by the far infrared radiation generator to the rotary drum, a radiation controller for controlling an amount of the radiant ray transmitted from the far infrared radiation generator to the rotary drum, and a convection fan for circulating air by rotating in forward and reverse direction depending on an internal temperature of the rotary drum.

Abstract: Disclosed herein is a pinnacle die structure having a scrap collecting opening. The pinnacle die structure comprises a pinnacle die(100), which includes a supporting plate(10) integrally formed with a cutter blade(20) and at least one hole-processing pin(30). The hole-processing pin is internally formed with a scrap discharge hole(32) to discharge a scrap(202) of a material sheet(200) punched by the pinnacle die. A scrap collecting opening(40) is defined above the hole-processing pin to collect the scrap discharged from the scrap discharge hole.

Abstract: A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.

Abstract: A method of forming a contact structure includes forming an isolation region defining active regions in a semiconductor substrate. Gate patterns extending to the isolation region while crossing the active regions are formed. A sacrificial layer is formed on the semiconductor substrate having the gate patterns. Sacrificial patterns remaining on the active regions are formed by patterning the sacrificial layer. Molding patterns are formed on the isolation region. Contact holes exposing the active regions at both sides of the gate patterns are formed by etching the sacrificial patterns using the molding patterns and the gate patterns as an etching mask. Contact patterns respectively filling the contact holes are formed. The disclosed method of forming a contact structure may be used in fabricating a semiconductor device.

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract: A semiconductor device with dummy patterns and methods of designing and making dummy patterns of a semiconductor device are provided. The method includes forming a first layout having main patterns, adding dot dummy patterns to the first layout to generate a second layout, and adding linked line/space dummy patterns to the second layout to generate a third layout. The dot dummy patterns may be oblique dot dummy patterns.

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The silicon nitride layer includes a plurality of bonds formed between silicon and nitrogen. A portion of the bonds formed between silicon and nitrogen is broken to form at least one free bonding site on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.

Abstract: In a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode including the quantum dot, a first layer including a first material is deposited on the substrate. The first material has first atoms that are superbundant and bound with the weak bonding energy in the first layer. A second layer is deposited on the first layer. The second layer comprises a second material including second atoms that are capable of migrating into the first atoms. The first atoms are migrated into the second layer and the second atoms are migrated into the first layer, so that the second atoms are arranged in the first layer. Each of the second atoms in the first layer is formed into a quantum dot. An electrode layer is formed on the first layer after partially etching the second layer, and then a gate electrode is formed by patterning the electrode layer.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The silicon nitride layer includes a plurality of bonds formed between silicon and nitrogen. A portion of the bonds formed between silicon and nitrogen is broken to form at least one free bonding site on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.

Abstract: In a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode including the quantum dot, a first layer including a first material is deposited on the substrate. The first material has first atoms that are superbundant and bound with the weak bonding energy in the first layer. A second layer is deposited on the first layer. The second layer comprises a second material including second atoms that are capable of migrating into the first atoms. The first atoms are migrated into the second layer and the second atoms are migrated into the first layer, so that the second atoms are arranged in the first layer. Each of the second atoms in the first layer is formed into a quantum dot. An electrode layer is formed on the first layer after partially etching the second layer, and then a gate electrode is formed by patterning the electrode layer.