Patents by Inventor Sun-Kyoung SEO
Sun-Kyoung SEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11610865Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: March 26, 2021Date of Patent: March 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Publication number: 20220077209Abstract: Provided is a semiconductor package. The semiconductor package includes an image sensor chip including a first surface and a second surface opposite to each other in a first direction; a transparent substrate spaced apart from the second surface of the image sensor chip in a second direction, wherein the transparent substrate includes a first part and a second part with a width different from the first part; an adhesive layer disposed between the second surface of the image sensor chip and the first part of the transparent substrate; and a mold layer on the second part of the transparent substrate, wherein the mold layer comprises side surfaces that extend along the first part of the transparent substrate, and further extend along side surfaces of the adhesive layer and side surfaces of the image sensor chip, and not extending along the first surface of the image sensor chip.Type: ApplicationFiled: April 15, 2021Publication date: March 10, 2022Inventors: Sun Jae Kim, Sun Kyoung Seo, Yong Hoe Cho
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Publication number: 20210217735Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: March 26, 2021Publication date: July 15, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Patent number: 10991677Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: April 14, 2020Date of Patent: April 27, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Patent number: 10867970Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: May 22, 2020Date of Patent: December 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Publication number: 20200286862Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Publication number: 20200243488Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Patent number: 10658341Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: June 21, 2019Date of Patent: May 19, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Publication number: 20190312013Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Patent number: 10373935Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: August 28, 2018Date of Patent: August 6, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Publication number: 20180374825Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: August 28, 2018Publication date: December 27, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Patent number: 10134702Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.Type: GrantFiled: April 24, 2017Date of Patent: November 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Seung-kwan Ryu, Cha-jea Jo, Tae-Je Cho
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Patent number: 10083939Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: January 31, 2017Date of Patent: September 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Patent number: 10008462Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.Type: GrantFiled: August 2, 2016Date of Patent: June 26, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Tae-je Cho, Yong-hwan Kwon, Hyung-gil Baek, Hyun-soo Chung, Seung-kwan Ryu, Myeong-soon Park
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Patent number: 9893018Abstract: Semiconductor devices and methods for manufacturing a semiconductor device include a first semiconductor substrate in which a first scribe line region and a first chip region are defined, a first alignment mark inside the first semiconductor substrate and in the first scribe line region so as to be spaced apart from an upper side of the first semiconductor substrate, a second semiconductor substrate on the first semiconductor substrate and in which a second scribe line region and a second chip region are defined, and a second alignment mark inside the second semiconductor substrate and in the second scribe line region so as to be spaced apart from an upper side of the second semiconductor substrate, wherein the second semiconductor substrate is on the first semiconductor substrate so that positions of the first alignment mark and the second alignment mark correspond to each other.Type: GrantFiled: May 14, 2015Date of Patent: February 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong-Kwon Ko, Tae-Hyeong Kim, Ji-Hwang Kim, Sun-Kyoung Seo, Tae-Je Cho
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Patent number: 9831202Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.Type: GrantFiled: September 12, 2016Date of Patent: November 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Seung-kwan Ryu, Ju-il Choi, Tae-je Cho, Yong-hwan Kwon
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Publication number: 20170338206Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: January 31, 2017Publication date: November 23, 2017Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Publication number: 20170229412Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Seung-kwan RYU, Cha-jea JO, Tae-Je CHO
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Publication number: 20170170136Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.Type: ApplicationFiled: August 15, 2016Publication date: June 15, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Seung-kwan RYU, Cha-jea JO, Tae-Je CHO
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Patent number: 9666551Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.Type: GrantFiled: August 15, 2016Date of Patent: May 30, 2017Assignee: Smasung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Seung-kwan Ryu, Cha-jea Jo, Tae-Je Cho