Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

Abstract: A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided.

Abstract: A semiconductor device, a semiconductor package, and a package stack structure include a semiconductor substrate, a first bonding pad disposed on a first surface of the semiconductor substrate, and a first pillar disposed on the first bonding pad. An upper surface of the first pillar has a concave shape. Side surfaces of the first pillar are substantially planar.

Abstract: A non-conductive material layer, selected from a non-conductive film and a non-conductive polymer paste, and containing a dispersion of zinc (Zn) particles is disclosed, together with semiconductor packages including the non-conductive material layer. The non-conductive material layer contains zinc (Zn) particles having an average particle diameter of about 1 nm to about 200 nm in a non-conductive polymer base material of a film type, and a semiconductor package includes the non-conductive film. By using the non-conductive film and/or the non-conductive paste containing the zinc dispersion, e a semiconductor package having excellent electric connection properties and high reliability may be manufactured through simple processes at low manufacturing costs.

Abstract: A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided.

Abstract: Semiconductor devices and methods for manufacturing a semiconductor device include a first semiconductor substrate in which a first scribe line region and a first chip region are defined, a first alignment mark inside the first semiconductor substrate and in the first scribe line region so as to be spaced apart from an upper side of the first semiconductor substrate, a second semiconductor substrate on the first semiconductor substrate and in which a second scribe line region and a second chip region are defined, and a second alignment mark inside the second semiconductor substrate and in the second scribe line region so as to be spaced apart from an upper side of the second semiconductor substrate, wherein the second semiconductor substrate is on the first semiconductor substrate so that positions of the first alignment mark and the second alignment mark correspond to each other.

Abstract: A semiconductor device, a semiconductor package, and a package stack structure include a semiconductor substrate, a first bonding pad disposed on a first surface of the semiconductor substrate, and a first pillar disposed on the first bonding pad. An upper surface of the first pillar has a concave shape. Side surfaces of the first pillar are substantially planar.

Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Abstract: A non-conductive material layer, selected from a non-conductive film and a non-conductive polymer paste, and containing a dispersion of zinc (Zn) particles is disclosed, together with semiconductor packages including the non-conductive material layer. The non-conductive material layer contains zinc (Zn) particles having an average particle diameter of about 1 nm to about 200 nm in a non-conductive polymer base material of a film type, and a semiconductor package includes the non-conductive film. By using the non-conductive film and/or the non-conductive paste containing the zinc dispersion, e a semiconductor package having excellent electric connection properties and high reliability may be manufactured through simple processes at low manufacturing costs.

Abstract: Provided are a stacked package, a method of fabricating a stacked package, and a method of mounting the stacked package fabricated by the same.

Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

Abstract: Provided are a stacked package, method of fabricating a stacked package, and method of mounting a stacked package. A method includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.

Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

Abstract: Provided are a stacked package, method of fabricating a stacked package, and method of mounting a stacked package. A method includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.

Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.