Abstract: Provided is a cooling system capable of effectively avoiding generation of bubbles in the flow passage including the piping unit that climbs over the barrier upon start of the pump that has been in the stopped state. The cooling system 100 includes a cooling tank 11 filled with a coolant C, flow passages 15, 16 through which the coolant discharged from an outlet of the cooling tank 11 returns to an inlet of the cooling tank 11, an inverted U-like piping unit 16a disposed in the middle of the flow passage 16, a main pump 31, an auxiliary pump 33 disposed opposite the main pump 31 while interposing the inverted U-like piping unit 16a with the main pump 31, and a controller 35 which controls driving operations of the main pump 31 and the auxiliary pump 33. The controller 35 drives the auxiliary pump 33 for a predetermined time period before starting the main pump 31.

Abstract: Provided is a cooling system capable of effectively avoiding generation of bubbles in the flow passage including the piping unit that climbs over the barrier upon start of the pump that has been in the stopped state. The cooling system 100 includes a cooling tank 11 filled with a coolant C, flow passages 15, 16 through which the coolant discharged from an outlet of the cooling tank 11 returns to an inlet of the cooling tank 11, an inverted U-like piping unit 16a disposed in the middle of the flow passage 16, a main pump 31, an auxiliary pump 33 disposed opposite the main pump 31 while interposing the inverted U-like piping unit 16a with the main pump 31, and a controller 35 which controls driving operations of the main pump 31 and the auxiliary pump 33. The controller 35 drives the auxiliary pump 33 for a predetermined time period before starting the main pump 31.

Abstract: Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small.

Abstract: A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

Abstract: A compression engine starts compressing data by a preset first compression rule, compresses the following data by a second compression rule when the characteristics of the data satisfy a predetermined switching condition, and returns to the first compression rule when the characteristics of the data do not satisfy the switching condition to compress the data and the following data. A decompression engine starts decompressing compressed data by a first decompression rule corresponding to the first compression rule, decompresses the following compressed data by a second decompression rule corresponding to the second compression rule when the characteristics of the data after decompression satisfy the switching condition, and returns to the first decompression rule when the characteristics of the data after decompression do not satisfy the switching condition to decompress the data and the following compressed data.

Abstract: A compression engine starts compressing data by a preset first compression rule, compresses the following data by a second compression rule when the characteristics of the data satisfy a predetermined switching condition, and returns to the first compression rule when the characteristics of the data do not satisfy the switching condition to compress the data and the following data. A decompression engine starts decompressing compressed data by a first decompression rule corresponding to the first compression rule, decompresses the following compressed data by a second decompression rule corresponding to the second compression rule when the characteristics of the data after decompression satisfy the switching condition, and returns to the first decompression rule when the characteristics of the data after decompression do not satisfy the switching condition to decompress the data and the following compressed data.

Abstract: A main functional structure executes continuous predetermined operations to continuously generate events associated with the operations. A debug/trace circuit compares an event occurring at the main functional structure with detection condition indicating information of one entry in a control information list, and executes the operation designated by operation indicating information paired with the detection condition indicating information in accordance with the result of the comparison. The debug/trace circuit continuously performs this in accordance with the control information list to identify the event.

Abstract: A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.

Abstract: Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small.

Abstract: A main functional structure executes continuous predetermined operations to continuously generate events associated with the operations. A debug/trace circuit compares an event occurring at the main functional structure with detection condition indicating information of one entry in a control information list, and executes the operation designated by operation indicating information paired with the detection condition indicating information in accordance with the result of the comparison. The debug/trace circuit continuously performs this in accordance with the control information list to identify the event.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

Abstract: A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least one shared resource. The multiple bus interfaces are connected to a multi-layer bus respectively. Furthermore, data buffers for holding read data and write data respectively are provided for each bus interface. An arbiter arbitrates access requests from the respective bus interfaces, and the shared resource reads and writes data in response to the access request which has been given an access right.

Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

Abstract: A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least one shared resource. The multiple bus interfaces are connected to a multi-layer bus respectively. Furthermore, data buffers for holding read data and write data respectively are provided for each bus interface. An arbiter arbitrates access requests from the respective bus interfaces, and the shared resource reads and writes data in response to the access request which has been given an access right.

Abstract: The data processing unit uses, for predetermined information processing, a series of data read by uniformly accessing a predetermined address range of the external storage device through the external interface. The determination unit determines whether to write the data read from the external storage device by the data processing unit to the internal storage unit or not and writes, to the internal storage unit, data determined to be written to the internal storage unit. When again reading data within the same address range of the external storage device, the data processing unit alternatively reads data from the internal storage unit.

Abstract: When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning success/failure results of the speculative execution of memory operation instructions of the past is referred to and thereby whether the speculative execution will succeed or fail is predicted. In the prediction, the target address of the memory operation instruction is converted by a hash function circuit into an entry number of the speculative execution result history table (allowing the existence of aliases), and an entry of the table designated by the entry number is referred to. If the prediction is “success”, the memory operation instruction is executed in out-of-order execution speculatively (with regard to data dependence relationship between the instructions).

Abstract: A program is divided into several instruction streams, and each of them is executed as a thread. A thread processor executed the thread. The thread generates another thread, but one thread is controlled to make a fork operation at most once. Each thread is terminated in the order of generations. A thread manager may be shared with the several thread processors or be distributed to the several thread processors. The thread manager includes a thread sequencer and a thread status table. The thread status table manages execution status of each thread processor and parent-child relation. The thread sequencer requests a thread generation and permits its termination in accordance with the content of the thread status table. The thread processor can execute a thread speculatively.