Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

Abstract: The data processing unit uses, for predetermined information processing, a series of data read by uniformly accessing a predetermined address range of the external storage device through the external interface. The determination unit determines whether to write the data read from the external storage device by the data processing unit to the internal storage unit or not and writes, to the internal storage unit, data determined to be written to the internal storage unit. When again reading data within the same address range of the external storage device, the data processing unit alternatively reads data from the internal storage unit.

Abstract: When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning success/failure results of the speculative execution of memory operation instructions of the past is referred to and thereby whether the speculative execution will succeed or fail is predicted. In the prediction, the target address of the memory operation instruction is converted by a hash function circuit into an entry number of the speculative execution result history table (allowing the existence of aliases), and an entry of the table designated by the entry number is referred to. If the prediction is “success”, the memory operation instruction is executed in out-of-order execution speculatively (with regard to data dependence relationship between the instructions).

Abstract: A program is divided into several instruction streams, and each of them is executed as a thread. A thread processor executed the thread. The thread generates another thread, but one thread is controlled to make a fork operation at most once. Each thread is terminated in the order of generations. A thread manager may be shared with the several thread processors or be distributed to the several thread processors. The thread manager includes a thread sequencer and a thread status table. The thread status table manages execution status of each thread processor and parent-child relation. The thread sequencer requests a thread generation and permits its termination in accordance with the content of the thread status table. The thread processor can execute a thread speculatively.

Abstract: The present invention provides a detector for detecting at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector is allowed to detect the at least one kind of dependence.

Abstract: A program is divided into several instruction streams, and each of them is executed as a thread. A thread processor executed the thread. The thread generates another thread, but one thread is controlled to make a fork operation at most once. Each thread is terminated in the order of generations. A thread manager may be shared with the several thread processors or be distributed to the several thread processors. The thread manager includes a thread sequencer and a thread status table. The thread status table manages execution status of each thread processor and parent-child relation. The thread sequencer requests a thread generation and permits its termination in accordance with the content of the thread status table. The thread processor can execute a thread speculatively.

Abstract: A register content inheriting system contributes for realization of register content inheriting with a hardware of simple construction in a multithread multi-processor. Respective thread execution units and physical common register are provided. Using a register mapping table, a register number to be made reference to from each program is placed in the physical common register. Only as required in inheriting of register content, a relationship of the register mapping table is updated. Upon inheriting the content of the register, the content of the register mapping table is copied.

Abstract: Disclosed is a cache coherency controller used in a multi-processor system. The cache coherency controller reflects a cache line including data produced by a preceding thread to a cache line including data produced by a succeeding thread. On the other hand, the cache coherency controller prevents a cache line including data produced by the succeeding thread from being reflected to the cache line including data produced by the preceding thread. The cache coherency controller maintains a sequential order (relationship) among threads based on a thread sequence information table and thereby maintains data anti-dependence.

Abstract: Each of a plurality of processors in a multi-processor system executes a thread. The processor includes an execution unit, a reorder buffer which temporally keeps the execution results by the execution unit, a register which stores the execution results kept in the reorder buffer in-order, and an instruction queue which issues an instruction to be executed by the execution queue to the execution queue, the instruction having gotten data necessary for the execution unit. After a thread generation instruction is issued from a parent thread in the processors, only data generated by an instruction prior to the thread generation instruction is inherited from the parent thread to a child thread.