Patents by Inventor Sundar Chetlur
Sundar Chetlur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220115316Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.Type: ApplicationFiled: October 9, 2020Publication date: April 14, 2022Applicant: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Cory Voisine, Kenneth Snowdon, Hsuan-Jung Wu
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Patent number: 11303116Abstract: An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.Type: GrantFiled: August 29, 2018Date of Patent: April 12, 2022Assignee: Allegro MicroSystems, LLCInventors: Washington Lamar, Maxim Klebanov, Sundar Chetlur
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Publication number: 20220077382Abstract: In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistance element (MRE) disposed over and coupled to the first layer through first vias. The MRE is magnetized to produce a first magnetic orientation. The first layer is disposed over and coupled to a second conductive layer in the circuit through second vias. The circuit also includes a metal filler disposed proximate to the MRE. The metal filler is positioned over and coupled to the second layer through third vias. The circuit also includes a thermal dissipation path resulting from a physical input applied to the first MRE. The thermal dissipation path extends through the first through third vias, the first and second layers, an integrated circuit interconnection, and the metal filler.Type: ApplicationFiled: September 8, 2020Publication date: March 10, 2022Applicant: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Paolo Campiglio, Yen Ting Liu
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Patent number: 11262385Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.Type: GrantFiled: May 24, 2019Date of Patent: March 1, 2022Assignee: Allegro MicroSystems, LLCInventors: Shaun D. Milano, Bryan Cadugan, Michael C. Doogue, Alexander Latham, William P. Taylor, Harianto Wong, Sundar Chetlur
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Patent number: 11195826Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.Type: GrantFiled: January 30, 2020Date of Patent: December 7, 2021Assignee: Allegro MicroSystems, LLCInventors: Maxim Klebanov, Washington Lamar, Sagar Saxena, Chung C. Kuo, Sebastian Courtney, Sundar Chetlur
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Patent number: 11170858Abstract: A method for use in a memory device including a first memory matrix is provided, the method comprising: receiving a write request that is associated with a first memory cell, the first memory cell being part of the first memory matrix; copying a content of a second memory cell into a register, the second memory cell being part of the first memory matrix; overwriting the second memory cell with the content of the register when the content of the second memory cell is different from the content of the register; and writing, to the first memory cell, at least a portion of data that is associated with the write request.Type: GrantFiled: March 18, 2020Date of Patent: November 9, 2021Assignee: Allegro MicroSystems, LLCInventors: Muhammad Sarwar, Vyankatesh Gupta, James McClay, Sundar Chetlur, Harianto Wong
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Publication number: 20210295932Abstract: A method for use in a memory device including a first memory matrix is provided, the method comprising: receiving a write request that is associated with a first memory cell, the first memory cell being part of the first memory matrix; copying a content of a second memory cell into a register, the second memory cell being part of the first memory matrix; overwriting the second memory cell with the content of the register when the content of the second memory cell is different from the content of the register; and writing, to the first memory cell, at least a portion of data that is associated with the write request.Type: ApplicationFiled: March 18, 2020Publication date: September 23, 2021Applicant: Allegro MicroSystems, LLCInventors: Muhammad Sarwar, Vyankatesh Gupta, James McClay, Sundar Chetlur, Harianto Wong
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Publication number: 20210242193Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.Type: ApplicationFiled: January 30, 2020Publication date: August 5, 2021Applicant: Allegro MicroSystems, LLCInventors: Maxim Klebanov, Washington Lamar, Sagar Saxena, Chung C. Kuo, Sebastian Courtney, Sundar Chetlur
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Publication number: 20210240606Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.Type: ApplicationFiled: February 5, 2020Publication date: August 5, 2021Applicant: Allegro MicroSystems, LLCInventors: Muhammed Sarwar, Vyankatesh Gupta, James McClay, Sundar Chetlur, Harianto Wong, Gerardo A. Monreal, Nicolás Rafael Biberidis, Octavio H. Alpago, Nicolas Rigoni
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Patent number: 11005036Abstract: A magnetoresistance structure includes a base that includes a conductive layer and a first active element on and in direct contact with the conductive layer. The magnetoresistance structure also includes a pillar structure connected to the base. The pillar structure includes a first hard mask, a capping material, a second active element and a tunnel layer. The magnetoresistance structure also further includes an etching barrier deposited on the pillar and the base; a second hard mask deposited on the etching barrier; and a capping barrier deposited on the second hard mask and covering side walls of the base.Type: GrantFiled: January 2, 2020Date of Patent: May 11, 2021Assignee: Allegro MicroSystems, LLCInventors: Yen Ting Liu, Maxim Klebanov, Paolo Campiglio, Sundar Chetlur
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Patent number: 10943976Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.Type: GrantFiled: August 12, 2019Date of Patent: March 9, 2021Assignee: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
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Publication number: 20210057642Abstract: An apparatus including a magnetoresistance element having conductive contacts disposed between the magnetoresistance element and a semiconductor substrate.Type: ApplicationFiled: November 5, 2020Publication date: February 25, 2021Applicant: Allegro MicroSystems, LLCInventors: Yen Ting Liu, Maxim Klebanov, Bryan Cadugan, Sundar Chetlur, Harianto Wong
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Patent number: 10916438Abstract: Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.Type: GrantFiled: May 9, 2019Date of Patent: February 9, 2021Assignee: Allegro MicroSystems, LLCInventors: Maxim Klebanov, Sundar Chetlur, James McClay
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Patent number: 10868240Abstract: A manufacturing method results in a magnetoresistance element having conductive contacts disposed between the magnetoresistance element and a semiconductor substrate.Type: GrantFiled: February 20, 2019Date of Patent: December 15, 2020Assignee: Allegro MicroSystems, LLCInventors: Yen Ting Liu, Maxim Klebanov, Bryan Cadugan, Sundar Chetlur, Harianto Wong
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Publication number: 20200357652Abstract: Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.Type: ApplicationFiled: May 9, 2019Publication date: November 12, 2020Applicant: Allegro MicroSystems, LLCInventors: Maxim Klebanov, Sundar Chetlur, James McClay
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Publication number: 20200266337Abstract: A manufacturing method results in a magnetoresistance element having conductive contacts disposed between the magnetoresistance element and a semiconductor substrate.Type: ApplicationFiled: February 20, 2019Publication date: August 20, 2020Applicant: Allegro MicroSystems, LLCInventors: Yen Ting Liu, Maxim Klebanov, Bryan Cadugan, Sundar Chetlur, Harianto Wong
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Publication number: 20200136032Abstract: A magnetoresistance structure includes a base that includes a conductive layer and a first active element on and in direct contact with the conductive layer. The magnetoresistance structure also includes a pillar structure connected to the base. The pillar structure includes a first hard mask, a capping material, a second active element and a tunnel layer. The magnetoresistance structure also further includes an etching barrier deposited on the pillar and the base; a second hard mask deposited on the etching barrier; and a capping barrier deposited on the second hard mask and covering side walls of the base.Type: ApplicationFiled: January 2, 2020Publication date: April 30, 2020Applicant: Allegro MicroSystems, LLCInventors: Yen Ting Liu, Maxim Klebanov, Paolo Campiglio, Sundar Chetlur
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Patent number: 10622549Abstract: Methods and apparatus for a signal isolator having a dielectric interposer supporting first and second die each having a magnetic field sensing element. A first signal path extends from the first die to the second die and a second signal path extends from the second die to the first die. In embodiments, the first signal path is located in the interposer and includes a first coil to generate a magnetic field and the second signal path is located in the interposer and includes a second coil to generate a magnetic filed. The first coil is located in relation to the second magnetic field sensing element of the second die and the second coil is located in relation to the first magnetic field sensing element of the first die.Type: GrantFiled: August 29, 2017Date of Patent: April 14, 2020Assignee: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Harianto Wong, Maxim Klebanov, William P. Taylor, Michael C. Doogue
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Publication number: 20200076189Abstract: An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.Type: ApplicationFiled: August 29, 2018Publication date: March 5, 2020Applicant: Allegro MicroSystems, LLCInventors: Washington Lamar, Maxim Klebanov, Sundar Chetlur
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Publication number: 20200075846Abstract: A method includes depositing on a substrate a magnetoresistance stack, depositing a first hard mask on the magnetoresistance stack, depositing a first photoresist on the first hard mask, patterning the first photoresist to expose portions of the first hard mask, and etching the exposed portions of the first hard mask to expose a portion of the magnetoresistance stack. The method further includes stripping the first photoresist, etching the exposed portions of the magnetoresistance stack and the first hard mask to form a first intermediate structure having a base and a pillar structure, depositing an etch barrier on the first intermediate structure, and depositing a second hard mask on the etch barrier. A second photoresist is deposited on the second hard mask.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Applicant: Allegro MicroSystems, LLCInventors: Yen Ting Liu, Maxim Klebanov, Paolo Campiglio, Sundar Chetlur