Patents by Inventor Sundar Chetlur
Sundar Chetlur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10566526Abstract: A method includes depositing on a substrate a magnetoresistance stack, depositing a first hard mask on the magnetoresistance stack, depositing a first photoresist on the first hard mask, patterning the first photoresist to expose portions of the first hard mask, and etching the exposed portions of the first hard mask to expose a portion of the magnetoresistance stack. The method further includes stripping the first photoresist, etching the exposed portions of the magnetoresistance stack and the first hard mask to form a first intermediate structure having a base and a pillar structure, depositing an etch barrier on the first intermediate structure, and depositing a second hard mask on the etch barrier. A second photoresist is deposited on the second hard mask.Type: GrantFiled: September 5, 2018Date of Patent: February 18, 2020Assignee: Allegro MicroSystems, LLCInventors: Yen Ting Liu, Maxim Klebanov, Paolo Campiglio, Sundar Chetlur
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Publication number: 20190363162Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.Type: ApplicationFiled: August 12, 2019Publication date: November 28, 2019Applicant: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
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Patent number: 10468485Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.Type: GrantFiled: May 26, 2017Date of Patent: November 5, 2019Assignee: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
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Publication number: 20190285667Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.Type: ApplicationFiled: May 24, 2019Publication date: September 19, 2019Applicant: Allegro MicroSystems, LLCInventors: Shaun D. Milano, Bryan Cadugan, Michael C. Doogue, Alexander Latham, William P. Taylor, Harianto Wong, Sundar Chetlur
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Patent number: 10352969Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.Type: GrantFiled: November 29, 2016Date of Patent: July 16, 2019Assignee: Allegro MicroSystems, LLCInventors: Shaun D. Milano, Bryan Cadugan, Michael C. Doogue, Alexander Latham, William P. Taylor, Harianto Wong, Sundar Chetlur
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Publication number: 20190067562Abstract: Methods and apparatus for a signal isolator having a dielectric interposer supporting first and second die each having a magnetic field sensing element. A first signal path extends from the first die to the second die and a second signal path extends from the second die to the first die. In embodiments, the first signal path is located in the interposer and includes a first coil to generate a magnetic field and the second signal path is located in the interposer and includes a second coil to generate a magnetic filed. The first coil is located in relation to the second magnetic field sensing element of the second die and the second coil is located in relation to the first magnetic field sensing element of the first die.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Harianto Wong, Maxim Klebanov, William P. Taylor, Michael C. Doogue
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Publication number: 20180342500Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.Type: ApplicationFiled: May 26, 2017Publication date: November 29, 2018Applicant: Allegro Microsystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
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Publication number: 20180149677Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Applicant: Allegro MicroSystems, LLCInventors: Shaun D. Milano, Bryan Cadugan, Michael C. Doogue, Alexander Latham, William P. Taylor, Harianto Wong, Sundar Chetlur
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Patent number: 9230861Abstract: A backside contact structure is created using the following sequence of steps: etching a deep trench from the front surface of the semiconductor wafer to the buried layer to be contacted; depositing an isolation layer into the trench which covers the surfaces of the trench; performing an ion beam anisotropic etch in order to selectively etch the isolation layer at the bottom of the trench; filling the trench with a conductive material in order to create an electrical connection to the backside layer. The process can either be performed at a front-end stage of wafer processing following the formation of shallow trench isolation structures, or at a back-end stage after device transistors are formed. The backside contact structure so fabricated is used to electrically isolate circuit structures constructed on the wafer's upper surface, so that the various components of an integrated circuit can operate at different reference voltages.Type: GrantFiled: October 9, 2013Date of Patent: January 5, 2016Assignee: Telefunken Semiconductors America LLCInventors: Sundar Chetlur, Guy Ng
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Publication number: 20140099772Abstract: A backside contact structure is created using the following sequence of steps: etching a deep tench from the front surface of the semiconductor wafer to the buried layer to be contacted; depositing an isolation layer into the trench which covers the surfaces of the trench; performing an ion beam anisotropic etch in order to selectively etch the isolation layer at the bottom of the trench; filling the trench with a conductive material in order to create an electrical connection to the backside layer. The process can either be performed at a front-end stage of wafer processing following the formation of shallow trench isolation structures, or at a back-end stage after device transistors are formed. The backside contact structure so fabricated is used to electrically isolate circuit structures constructed on the wafer's upper surface, so that the various components of an integrated circuit can operate at different reference voltages.Type: ApplicationFiled: October 9, 2013Publication date: April 10, 2014Inventors: Sundar Chetlur, Guy Ng
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Patent number: 6664800Abstract: A non-contact method for determining a quality of a semiconductor dielectric. The method includes depositing a charge on a dielectric to achieve a high voltage on the dielectric, measuring a voltage drop of the dielectric as a function of time, and determining a soft breakdown voltage of the dielectric from the voltage drop as a function of time. The amount of charge that is deposited may vary. For example, the charge may be deposited until a voltage that ranges from about 4 megavolts to about 16 megavolts is achieved on the dielectric. The amount of charge may also depend on the thickness of the dielectric. For example, applying a charge as a function of the thickness may include applying 4 megavolts when the thickness is about 1.2 nm or applying 16 megavolts when the thickness is about 5.0 nm.Type: GrantFiled: January 8, 2001Date of Patent: December 16, 2003Assignee: Agere Systems Inc.Inventors: Carlos M. Chacon, Sundar Chetlur, Pradip K. Roy
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Patent number: 6605529Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.Type: GrantFiled: May 11, 2001Date of Patent: August 12, 2003Assignee: Agere Systems Inc.Inventors: Sundar Chetlur, Jennifer M. McKinley, Minesh A. Patel, Pradip K. Roy, Jonathan Zhong-Ning Zhou
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Publication number: 20020168841Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.Type: ApplicationFiled: May 11, 2001Publication date: November 14, 2002Inventors: Sundar Chetlur, Jennifer M. McKinley, Minesh A. Patel, Pradip K. Roy, Jonathan Zhong-Ning Zhou
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Publication number: 20020121914Abstract: The present invention provides a non-contact method for determining a quality of a semiconductor dielectric. The method includes depositing a charge on a dielectric to achieve a high voltage on the dielectric, measuring a voltage drop of the dielectric as a function of time, and determining soft breakdown of the dielectric from the voltage drop as a function of time. The amount of charge that is deposited may vary. For example, the charge may be deposited until a voltage that ranges from about 4 megavolts to about 16 megavolts is achieved on the dielectric. The amount of charge may also depend on the thickness of the dielectric. For example, applying a charge as a function of the thickness may include applying 4 megavolts when the thickness is about 1.2 nm or applying 16 megavolts when the thickness is about 5.0 nm.Type: ApplicationFiled: January 8, 2001Publication date: September 5, 2002Inventors: Carlos M. Chacon, Sundar Chetlur, Pradip K. Roy
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Patent number: 6198301Abstract: The present invention provides a method for determining a hot carrier lifetime of a transistor. In one embodiment, the method comprises the steps of determining an initial transconductance (gm1) of a transistor, and then, applying a stress voltage, which does not exceed a maximum breakdown voltage of the transistor, to the transistor to cause a transconductance degradation of the transistor, and then determining a subsequent transconductance (gm2) of the transistor. A hot carrier lifetime of the transistor can then be determined as a function of gm1 and gm2. Thus, the present invention provides a method in which the hot carrier lifetime is determined from sequential transconductance measurements without intervening, transistor characteristic tests that are typically conducted between the transconductance measurements that degrade the sensitivity of the gm measurement.Type: GrantFiled: July 23, 1998Date of Patent: March 6, 2001Assignee: Lucent Technologies Inc.Inventors: Sundar Chetlur, Merlyne M. De Souza, Anthony S. Oates